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HD64F36049 Datasheet(PDF) 25 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 25 Page - Renesas Technology Corp |
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25 / 562 page  Rev. 3.00 Mar. 15, 2006 Page xxv of xxxii Figure 14.38 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register).................................................. 270 Figure 14.39 Example of Compare Match Timing for Buffer Operation ................................... 271 Figure 14.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) ...................................................... 272 Figure 14.41 Input Capture Timing of Buffer Operation............................................................ 273 Figure 14.42 Buffer Operation (3) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............ 274 Figure 14.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............ 275 Figure 14.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 276 Figure 14.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 277 Figure 14.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 277 Figure 14.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 278 Figure 14.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 279 Figure 14.49 IMF Flag Set Timing at Input Capture .................................................................. 279 Figure 14.50 OVF Flag Set Timing ............................................................................................ 280 Figure 14.51 Status Flag Clearing Timing.................................................................................. 280 Figure 14.52 Contention between TCNT Write and Clear Operations....................................... 281 Figure 14.53 Contention between TCNT Write and Increment Operations ............................... 281 Figure 14.54 Contention between GR Write and Compare Match ............................................. 282 Figure 14.55 Contention between TCNT Write and Overflow................................................... 283 Figure 14.56 Contention between GR Read and Input Capture.................................................. 284 Figure 14.57 Contention between Count Clearing and Increment Operations by Input Capture .................................................................................................................. 285 Figure 14.58 Contention between GR Write and Input Capture................................................. 286 Figure 14.59 When Compare Match and Bit Manipulation Instruction to TOCR Occur at the Same Timing ......................................................................................................... 287 Section 15 Watchdog Timer Figure 15.1 Block Diagram of Watchdog Timer ........................................................................ 289 Figure 15.2 Watchdog Timer Operation Example...................................................................... 293 Section 16 14-Bit PWM Figure 16.1 Block Diagram of 14-Bit PWM .............................................................................. 295 Figure 16.2 Waveform Output by 14-Bit PWM ......................................................................... 298 Section 17 Serial Communication Interface 3 (SCI3) Figure 17.1 Block Diagram of SCI3........................................................................................... 302 Figure 17.2 Data Format in Asynchronous Communication ...................................................... 318 Figure 17.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 318 |
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