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HD64F36049 Datasheet(PDF) 88 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 88 Page - Renesas Technology Corp |
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88 / 562 page ![]() Section 3 Exception Handling Rev. 3.00 Mar. 15, 2006 Page 56 of 526 REJ09B0060-0300 WKP5 to WKP0 Interrupts: WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2. When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by setting bit IENWP in IENR1. Vector fetch Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) RES Internal processing Prefetch of first program instruction φ (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset vector) (5) Start address (6) First instruction of program (1) (3) (5) (2) (4) (6) Figure 3.1 Reset Sequence |
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