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HD64F36049 Datasheet(PDF) 90 Page - Renesas Technology Corp |
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HD64F36049 Datasheet(HTML) 90 Page - Renesas Technology Corp |
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90 / 562 page  Section 3 Exception Handling Rev. 3.00 Mar. 15, 2006 Page 58 of 526 REJ09B0060-0300 Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. PC and CCR saved to stack SP (ER7) SP – 1 SP – 2 SP – 3 SP – 4 Stack area SP + 4 SP + 3 SP + 2 SP + 1 SP (ER7) Even address Prior to start of interrupt exception handling After completion of interrupt exception handling [Legend] PCE: PCH: PCL: CCR: SP: Bits 23 to 16 of program counter (PC) Bits 15 to 8 of program counter (PC) Bits 7 to 0 of program counter (PC) Condition code register Stack pointer Notes: CCR PCE PCH PCL 1. 2. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. Register contents must always be saved and restored by word length, starting from an even-numbered address. Figure 3.2 Stack Status after Exception Handling |
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