SH7101 datasheet(348/486 Pages) RENESAS

348 / 486 page

10. Serial Communication Interface (SCI)

Rev.2.00 Sep. 27, 2007 Page 314 of 448

REJ09B0394-0200

10.6.2

SCI Initialization (Clocked Synchronous Mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then

initialize the SCI as described in a sample flowchart in figure 10.15. When the operating mode,

transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the

change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.

Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or the

contents of RDR.

Wait

Yes

Start initialization

Set data transfer format in

SMR

Set value in BRR

Clear RIE, TIE, TEIE, MPIE,

TE and RE bits in SCR to 0*

[2]

[3]

Set the RIE, TIE, TEIE, and

MPIE bits in SCR

[4]

[5]

[6]

1-bit interval elapsed?

Set PFC of the external pin used

SCK, TxD, RxD

Set TE and RE bits of SCR to 1

Set CKE1 and CKE0 bits in SCR

(TE and RE bits are 0)

[1]

[1] Set the clock selection in SCR.

[2] Set the data transfer format in SMR.

[3] Write a value corresponding to the bit

rate to BRR. Not necessary if an

external clock is used.

[4] Set the RIE, TIE TEIE, and MPIE bits.

[5] Set PFC of the external pin used. Set

RxD input during receiving and TxD

output during transmitting. Set SCK

input/output according to contents set

by CKE1 and CKE0.

[6] Wait at least one bit interval, then set

the TE bit or RE bit in SCR to 1.* At this

time, the TxD, RxD, and SCK pins can

be used. The TxD pin is in a mark state

during transmitting. When synchronous

clock output (clock master) is set during

receiving in synchronous mode,

outputting clocks from the SCK pin

starts.

Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be

cleared to 0 or set to 1 simultaneously.

Figure 10.15 Sample SCI Initialization Flowchart

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