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SH7101 Datasheet(PDF) 46 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 46 Page - Renesas Technology Corp |
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46 / 486 page ![]() 2. CPU Rev.2.00 Sep. 27, 2007 Page 12 of 448 REJ09B0394-0200 31 0 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 General registers (Rn) Status register (SR) Global base register (GBR) Vector base register (VBR) Multiply-accumulate register (MAC) Procedure register (PR) Program counter (PC) 31 9 8 7 6 5 4 3 2 1 0 0 0 31 M GBR 31 VBR QI3 I2 I1 I0 S T 31 0 MACH 31 0 PR 31 0 PC MACL Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 CPU Internal Registers |
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