SH7101 datasheet(35/486 Pages) RENESAS

35 / 486 page

1. Overview

Rev.2.00 Sep. 27, 2007 Page 1 of 448

REJ09B0394-0200

Section 1 Overview

The SH7101 single-chip RISC (Reduced Instruction Set Computer) microcomputer integrates a

Renesas Technology-original RISC CPU core with peripheral functions required for system

configuration.

The SH7101 CPU has a RISC-type instruction set. Most instructions can be executed in one state

(one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-

bit internal-bus architecture enhances data processing power. With this CPU, it has become

possible to assemble low cost, high performance/high-functioning systems, even for applications

that were previously impossible with microcomputers, such as real-time control, which demands

high speeds.

In addition, the SH7101 includes on-chip peripheral functions necessary for system configuration,

such as ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an

interrupt controller (INTC), and I/O ports.

As the on-chip ROM, only mask ROM version is available. However, when F-ZTAT

TM (Flexible

Zero Turn Around Time) version is required, the SH7046F can be used.

1.1

Features

• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer)

architecture

⎯ Instruction length: 16-bit fixed length for improved code efficiency

⎯ Load-store architecture (basic operations are executed between registers)

⎯ Sixteen 32-bit general registers

⎯ Five-stage pipeline

⎯ On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two

to four cycles

⎯ C language-oriented 62 basic instructions

• Various peripheral functions

⎯ Multifunction timer/pulse unit (MTU)

⎯ Compare match timer (CMT)

⎯ Watchdog timer (WDT)

⎯ Asynchronous or clocked synchronous serial communication interface (SCI)

⎯ 10-bit A/D converter

⎯ Clock pulse generator

SH7101 Datasheet(PDF) 35 Page - Renesas Technology Corp