SH7101 datasheet(25/486 Pages) RENESAS

25 / 486 page

Rev.2.00 Sep. 27, 2007 Page xxv of xxxiv

REJ09B0394-0200

Figure 8.52

Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)... 190

Figure 8.53

Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)... 191

Figure 8.54

Count Timing in Internal Clock Operation............................................................. 195

Figure 8.55

Count Timing in External Clock Operation ........................................................... 195

Figure 8.56

Count Timing in External Clock Operation (Phase Counting Mode)..................... 196

Figure 8.57

Output Compare Output Timing (Normal Mode/PWM Mode).............................. 196

Figure 8.58

Output Compare Output Timing

(Complementary PWM Mode/Reset Synchronous PWM Mode) .......................... 197

Figure 8.59

Input Capture Input Signal Timing......................................................................... 197

Figure 8.60

Counter Clear Timing (Compare Match) ............................................................... 198

Figure 8.61

Counter Clear Timing (Input Capture) ................................................................... 198

Figure 8.62

Buffer Operation Timing (Compare Match) .......................................................... 199

Figure 8.63

Buffer Operation Timing (Input Capture) .............................................................. 199

Figure 8.64

TGI Interrupt Timing (Compare Match) ................................................................ 200

Figure 8.65

TGI Interrupt Timing (Input Capture) .................................................................... 201

Figure 8.66

TCIV Interrupt Setting Timing............................................................................... 202

Figure 8.67

TCIU Interrupt Setting Timing............................................................................... 202

Figure 8.68

Timing for Status Flag Clearing by the CPU ......................................................... 203

Figure 8.69

Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................. 204

Figure 8.70

Contention between TCNT Write and Clear Operations........................................ 205

Figure 8.71

Contention between TCNT Write and Increment Operations ................................ 206

Figure 8.72

Contention between TGR Write and Compare Match ........................................... 207

Figure 8.73

Contention between Buffer Register Write and Compare Match (Channel 0) ....... 208

Figure 8.74

Contention between Buffer Register Write and Compare Match

(Channels 3 and 4).................................................................................................. 209

Figure 8.75

Contention between TGR Read and Input Capture ................................................ 210

Figure 8.76

Contention between TGR Write and Input Capture ............................................... 211

Figure 8.77

Contention between Buffer Register Write and Input Capture............................... 212

Figure 8.78

TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection.. 213

Figure 8.79

Counter Value during Complementary PWM Mode Stop ..................................... 214

Figure 8.80

Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode.............. 215

Figure 8.81

Reset Sync PWM Mode Overflow Flag ................................................................. 216

Figure 8.82

Contention between Overflow and Counter Clearing ............................................ 217

Figure 8.83

Contention between TCNT Write and Overflow.................................................... 218

Figure 8.84

Error Occurrence in Normal Mode, Recovery in Normal Mode ............................ 223

Figure 8.85

Error Occurrence in Normal Mode, Recovery in PWM Mode 1............................ 224

Figure 8.86

Error Occurrence in Normal Mode, Recovery in PWM Mode 2............................ 225

Figure 8.87

Error Occurrence in Normal Mode, Recovery in Phase Counting Mode ............... 226

Figure 8.88

Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode .... 227

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