SH7101 datasheet(8/486 Pages) RENESAS

8 / 486 page

Rev.2.00 Sep. 27, 2007 Page viii of xxxiv

REJ09B0394-0200

Item

Page

Revision (See Manual for Details)

8.4.4 Cascaded

Operation

Figure 8.18 Cascaded

Operation Setting

Procedure

149

Figure amended

[1] Set bits TPSC2 to TPSC0 in the channel 1

TCR to B'111 to select TCNT_2 overflow/ underflow

counting.

8.4.8 Complementary

PWM Mode

Example of

Complementary PWM

Mode Setting

Procedure:

170

Description amended

10. Set enabling/disabling of PWM waveform output pin output

in the timer output master enable register (TOER).

11. Set bits CST3 and CST4 in TSTR to 1 simultaneously to

start the count operation.

Complementary PWM

Mode Output Protection

Function:

192

Description amended

• Register and counter miswrite prevention function

With the exception of the buffer registers, which can be

rewritten at any time, access by the CPU can be enabled or

disabled for the mode registers, control registers, compare

registers, and counters used in complementary PWM mode by

means of bit 13 in the bus controller's bus control register 1

(BCR1). Some registers in channels 3 and 4 concerned are

listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3

and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and

TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4;

TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR;

TGCR; TCDR; and TDDR. This function enables the CPU to

prevent miswriting due to the CPU runaway by disabling CPU

access to the mode registers, control registers, and counters. In

access disabled state, an undefined value is read from the

registers concerned, and cannot be modified.

8.5.1 Interrupts and

Priorities

Underflow Interrupt:

194

Description amended

An interrupt is requested if the TCIEU bit in TIER is set to 1

when the TCFU flag in TSR is set to 1 by the occurrence of

TCNT underflow on a channel. The interrupt request is cleared

by clearing the TCFU flag to 0. The MTU has two underflow

interrupts, one each for channels 1 and 2.

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