SH7101 datasheet(15/486 Pages) RENESAS

15 / 486 page

Rev.2.00 Sep. 27, 2007 Page xv of xxxiv

REJ09B0394-0200

6.3

Register Descriptions ...........................................................................................................68

6.3.1

Interrupt Control Register 1 (ICR1) ........................................................................ 69

6.3.2

Interrupt Control Register 2 (ICR2) ........................................................................ 70

6.3.3

IRQ Status Register (ISR)....................................................................................... 72

6.3.4

Interrupt Priority Registers A, D to I (IPRA, IPRD to IPRI) .................................. 73

6.4

Interrupt Sources .................................................................................................................. 75

6.4.1

External Interrupts .................................................................................................. 75

6.4.2

On-Chip Peripheral Module Interrupts ................................................................... 77

6.5

Interrupt Exception Processing Vectors Table..................................................................... 77

6.6

Operation.............................................................................................................................. 81

6.6.1

Interrupt Sequence .................................................................................................. 81

6.6.2

Stack after Interrupt Exception Processing ............................................................. 83

6.7

Interrupt Response Time ...................................................................................................... 84

Section 7 Bus State Controller (BSC)................................................................. 87

7.1

Features ................................................................................................................................ 87

7.2

Input/output Pin.................................................................................................................... 87

7.3

Register ................................................................................................................................ 87

7.4

Address Map ........................................................................................................................ 88

7.5

Register Description............................................................................................................. 89

7.5.1

Bus Control Register 1 (BCR1) .............................................................................. 89

7.6

On-chip Peripheral I/O Register Access .............................................................................. 90

Section 8 Multi-Function Timer Pulse Unit (MTU) ........................................... 91

8.1

Features ................................................................................................................................ 91

8.2

Input/Output Pins ................................................................................................................. 95

8.3

Register Descriptions ...........................................................................................................96

8.3.1

Timer Control Register (TCR) ................................................................................ 98

8.3.2

Timer Mode Register (TMDR) ............................................................................. 102

8.3.3

Timer I/O Control Register (TIOR) ...................................................................... 104

8.3.4

Timer Interrupt Enable Register (TIER) ............................................................... 122

8.3.5

Timer Status Register (TSR)................................................................................. 124

8.3.6

Timer Counter (TCNT)......................................................................................... 126

8.3.7

Timer General Register (TGR) ............................................................................. 127

8.3.8

Timer Start Register (TSTR)................................................................................. 127

8.3.9

Timer Synchro Register (TSYR) .......................................................................... 128

8.3.10 Timer Output Master Enable Register (TOER) .................................................... 130

8.3.11 Timer Output Control Register (TOCR) ............................................................... 131

8.3.12 Timer Gate Control Register (TGCR)................................................................... 133

8.3.13 Timer Subcounter (TCNTS) ................................................................................. 135

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