SH7101 datasheet(64/486 Pages) RENESAS

64 / 486 page

2. CPU

Rev.2.00 Sep. 27, 2007 Page 30 of 448

REJ09B0394-0200

Table 2.11

Symbols Used in Instruction Code, Operation, and Execution States Tables

Item

Format

Explanation

Instruction

Described in

mnemonic.

OP.Sz SRC,DEST

OP: Operation code

Sz: Size

SRC: Source

DEST: Destination

Rm: Source register

Rn: Destination register

imm: Immediate data

disp: Displacement*2

Instruction

code

Described in MSB

↔

LSB order

mmmm: Source register

nnnn: Destination register

0000: R0

0001: R1

⋅

1111: R15

iiii: Immediate data

dddd: Displacement

→, ←

Direction of transfer

(xx)

Memory operand

M/Q/T

Flag bits in the SR

Logical AND of each bit

Logical OR of each bit

Exclusive OR of each bit

Logical NOT of each bit

<<n

n-bit left shift

Outline of the

Operation

>>n

n-bit right shift

Execution

states

⎯

Value when no wait states are inserted*1

T bit

⎯

Value of T bit after instruction is executed. An em-dash (

⎯)

in the column means no change.

Notes: 1. Instruction execution states: The execution states shown in the table are minimums.

The actual number of states may be increased when (1) contention occurs between

instruction fetches and data access, or (2) when the destination register of the load

instruction (memory

→ register) equals to the register used by the next instruction.

2. Depending on the operand size, displacement is scaled by

×1, ×2, or ×4. For details,

refer the SH-1/SH-2/SH-DSP Software Manual.

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