SH7101 datasheet(68/486 Pages) RENESAS

68 / 486 page

2. CPU

Rev.2.00 Sep. 27, 2007 Page 34 of 448

REJ09B0394-0200

Instruction

Instruction Code

Operation

Execu-

tion

States

T Bit

DIV0U

0000000000011001

→ M/Q/T

DMULS.L Rm,Rn

0011nnnnmmmm1101

Signed operation of

× Rm → MACH,

MACL 32

× 32 → 64 bits

2 to 4*

⎯

DMULU.L Rm,Rn

0011nnnnmmmm0101

Unsigned operation of

× Rm → MACH,

MACL 32

× 32 → 64 bits

2 to 4*

⎯

0100nnnn00010000

Rn – 1

→ Rn, when Rn

is 0, 1

→ T. When Rn is

nonzero, 0

→ T

Comparison

result

EXTS.B

Rm,Rn

0110nnnnmmmm1110

Byte in Rm is sign-

extended

→ Rn

⎯

EXTS.W

Rm,Rn

0110nnnnmmmm1111

Word in Rm is sign-

extended

→ Rn

⎯

EXTU.B

Rm,Rn

0110nnnnmmmm1100

Byte in Rm is zero-

extended

→ Rn

⎯

EXTU.W

Rm,Rn

0110nnnnmmmm1101

Word in Rm is zero-

extended

→ Rn

⎯

MAC.L

@Rm+,@Rn+

0000nnnnmmmm1111

Signed operation of

(Rn)

× (Rm) + MAC →

MAC 32

× 32 + 64 →

64 bits

(2 to 4)*

⎯

MAC.W

@Rm+,@Rn+

0100nnnnmmmm1111

Signed operation of

(Rn)

× (Rm) + MAC →

MAC 16

× 16 + 64 →

64 bits

3/(2)*

⎯

MUL.L

Rm,Rn

0000nnnnmmmm0111

× Rm → MACL,

× 32 → 32 bits

2 to 4*

⎯

MULS.W

Rm,Rn

0010nnnnmmmm1111

Signed operation of

× Rm → MACL 16 ×

→ 32 bits

1 to 3*

⎯

MULU.W

Rm,Rn

0010nnnnmmmm1110

Unsigned operation of

× Rm → MACL 16 ×

→ 32 bits

1 to 3*

⎯

NEG

Rm,Rn

0110nnnnmmmm1011

0 – Rm

→ Rn

⎯

NEGC

Rm,Rn

0110nnnnmmmm1010

0 – Rm – T

→ Rn,

Borrow

→ T

Borrow

SH7101 Datasheet(PDF) 68 Page - Renesas Technology Corp

SH7101 Datasheet(HTML) 68 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL