SH7101 datasheet(40/486 Pages) RENESAS

40 / 486 page

1. Overview

Rev.2.00 Sep. 27, 2007 Page 6 of 448

REJ09B0394-0200

Type

Symbol

I/O

Name

Function

Operating

mode control

FWP

Input

Protection

against write

operation into

Flash memory

Pin for the flash memory. This pin is only

used in the flash memory version. Writing

or erasing of flash memory can be

protected. This pin becomes the Vcc pin

for the mask ROM version.

System

control

RES

Input

Power on

reset

When this pin is driven low, the chip

becomes to power on reset state.

MRES

Input

Manual reset

When this pin is driven low, the chip

becomes to manual reset state.

WDTOVF

Output

Watchdog

timer overflow

Output signal for the watchdog timer

overflow. This pin should be pulled down

with at least 1 M

Ω resistor value.

NMI

Input

Non-maskable

interrupt

Non-maskable interrupt pin. If this pin is

not used, it should be fixed high or low.

IRQ3 to IRQ0 Input

Interrupt

request 3 to 0

These pins request a maskable interrupt.

One of the level input or edge input can be

selected. In case of the edge input, one of

the rising edge, falling edge, or both can

be selected.

Interrupts

IRQOUT

Output

Interrupt

request output

Shows that an interrupt cause has

occurred.

Multi function

timer-pulse

unit (MTU)

TCLKA

TCLKB

TCLKC

TCLKD

Input

External clock

input for MTU

timer

These pins input an external clock.

TIOC0A

TIOC0B

TIOC0C

TIOC0D

Input/

Output

MTU input

capture/output

compare

(channel 0)

The TGRA_0 to TGRD_0 input capture

input/output compare output/PWM output

pins.

TIOC1A

TIOC1B

Input/

Output

MTU input

capture/output

compare

(channel 1)

The TGRA_1 to TGRB_1 input capture

input/output compare output/PWM output

pins.

TIOC2A

TIOC2B

Input/

Output

MTU input

capture/output

compare

(channel 2)

The TGRA_2 to TGRB_2 input capture

input/output compare output/PWM output

pins.

SH7101 Datasheet(PDF) 40 Page - Renesas Technology Corp

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