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SH7101 Datasheet(PDF) 57 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  486 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 57 Page - Renesas Technology Corp

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2. CPU
Rev.2.00 Sep. 27, 2007 Page 23 of 448
REJ09B0394-0200
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
PC relative
addressing
Rn
The effective address is the sum of the register PC
and Rn.
PC
Rn
PC + Rn
+
PC + Rn
Immediate
addressing
#imm:8
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
⎯
#imm:8
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions is sign-extended.
⎯
#imm:8
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
⎯



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