SH7101 datasheet(47/486 Pages) RENESAS

47 / 486 page

2. CPU

Rev.2.00 Sep. 27, 2007 Page 13 of 448

REJ09B0394-0200

2.2.1

General Registers (Rn)

The sixteen 32-bit general registers (Rn) are numbered R0 to R15. General registers are used for

data processing and address calculation. R0 is also used as an index register. Several instructions

have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving

and recovering the status register (SR) and program counter (PC) in exception processing is

accomplished by referencing the stack using R15.

2.2.2

Control Registers

The control registers consist of three 32-bit registers: status register (SR), global base register

(GBR), and vector base register (VBR). The status register indicates processing states. The global

base register functions as a base address for the indirect GBR addressing mode to transfer data to

the registers of on-chip peripheral modules. The vector base register functions as the base address

of the exception processing vector area (including interrupts).

Status Register (SR):

Bit

Bit Name

Initial

Value

R/W

Description

31 to 10

⎯

All 0

R/W

Reserved

This bit is always read as 0. The write value should

always be 0.

Undefined

R/W

Used by the DIV0U, DIV0S, and DIV1 instructions.

Undefined

R/W

Used by the DIV0U, DIV0S, and DIV1 instructions.

R/W

Interrupt mask bits.

3, 2

⎯

All 0

R/W

Reserved

This bit is always read as 0. The write value should

always be 0.

Undefined

R/W

S bit

Used by the MAC instruction.

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