SH7101 datasheet(74/486 Pages) RENESAS

74 / 486 page

2. CPU

Rev.2.00 Sep. 27, 2007 Page 40 of 448

REJ09B0394-0200

Instruction

Instruction Code

Operation

Execu-

tion

States

T Bit

STS

MACH,Rn

0000nnnn00001010

MACH

→ Rn

⎯

STS

MACL,Rn

0000nnnn00011010

MACL

→ Rn

⎯

STS

PR,Rn

0000nnnn00101010

→ Rn

⎯

STS.L

MACH,@–Rn

0100nnnn00000010

Rn – 4

→ Rn, MACH → (Rn)

⎯

STS.L

MACL,@–Rn

0100nnnn00010010

Rn – 4

→ Rn, MACL → (Rn)

⎯

STS.L

PR,@–Rn

0100nnnn00100010

Rn – 4

→ Rn, PR → (Rn)

⎯

TRAPA

#imm

11000011iiiiiiii

PC/SR

→ stack area, (imm × 4

+ VBR)

→ PC

⎯

Note:

The number of execution states before the chip enters sleep mode: The execution

states shown in the table are minimums. The actual number of states may be increased

when (1) contention occurs between instruction fetches and data access, or (2) when

the destination register of the load instruction (memory

→ register) equals to the

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