SH7101 datasheet(7/486 Pages) RENESAS

7 / 486 page

Rev.2.00 Sep. 27, 2007 Page vii of xxxiv

REJ09B0394-0200

Main Revisions for This Edition

Item

Page

Revision (See Manual for Details)

All

⎯

• Company name and brand names amended

(Before) Hitachi, Ltd.

→ (After) Renesas Technology Corp.

6.5 Interrupt Exception

Processing Vectors

Table

Table 6.2 Interrupt

Exception Processing

Vectors and Priorities

Table amended

Interrupt

Source

Name

MTU channel 3 TGIA_3

TGIB_3

TGIC_3

TGID_3

TCIV_3

7.5.1 Bus Control

Bit table amended

Bit

Bit Name

Initial

Value

R/W

Description

⎯

Reserved

These bits are always read as 1 and should always be

written to 1.

8.1 Features

Figure 8.1 Block

Diagram of MTU

Title and figure amended

Interrupt request signals

Channel 3:

Channel 4:

TGI3A

TGI3B

TGI3C

TGI3D

TCI3V

TGI4A

TGI4B

TGI4C

TGI4D

TCI4V

8.3.3 Timer I/O Control

Table 8.13 TIORL_0

(channel 0)

109

Table amended

Description

Bit 3

IOC3

Bit 2

IOC2

Bit 1

IOC1

Bit 0

IOC0

TGRC_0

Function

TIOC0C Pin Function

Output disable

Output

compare

Initial output is 0

0 output at compare match

8.4.4 Cascaded

Operation

Table 8.30 Cascaded

Combinations

149

Note amended

Note: When phase counting mode is set for channel 1 or 2, the

counter clock setting is invalid and the counters operates

independently in phase counting mode.

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