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SH7101 Datasheet(PDF) 37 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 37 Page - Renesas Technology Corp |
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37 / 486 page  1. Overview Rev.2.00 Sep. 27, 2007 Page 3 of 448 REJ09B0394-0200 1.2 Internal Block Diagram : Peripheral address bus (12 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVcL PLLCAP PLLVss FWP VcL VcL Vcc Vcc Vcc Vss Vss Vss Vss AVcc AVcc AVss AVss Serial communication interface ( ×2 channels) Multifunction timer pulse unit Interrupt controller Bus state controller Compare match timer ( ×2 channels) A/D converter Watchdog timer Mask ROM 32 kbytes CPU RAM 2 kbytes PLL Figure 1.1 Internal Block Diagram of SH7101 |
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