SH7101 datasheet(83/486 Pages) RENESAS

83 / 486 page

4. Clock Pulse Generator

Rev.2.00 Sep. 27, 2007 Page 49 of 448

REJ09B0394-0200

4.1.2

External Clock Input Method

Figure 4.4 shows an example of an external clock input connection. In this case, make the external

clock high level to stop it in standby mode. During operation, make the external input clock

frequency 4 to 10 MHz.

When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF.

Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in

power-on sequence or in releasing standby mode, in order to ensure the PLL stabilization time.

EXTAL

XTAL

External clock input

Open state

Figure 4.4 Example of External Clock Connection

4.2

Function for Detecting Oscillator Halt

This CPG can detect a clock halt and automatically cause the timer pins to become high-

impedance when any system abnormality causes the oscillator to halt. That is, when a change of

EXTAL has not been detected, the high-current six pins (PE9/TIOC3B, PE11/TIOC3D,

PE12/TIOC4A, PE13/TIOC4B/

MRES, PE14/TIOC4C, and PE15/TIOC4D/IRQOUT) are set to

high-impedance regardless of PFC setting.

Even in standby mode, these six pins become high-impedance regardless of PFC setting. These

pins enter the normal state after standby mode is released. When abnormalities that halt the

oscillator occur except in standby mode, other LSI operations become undefined. In this case, LSI

operations, including these six pins, become undefined even when the oscillator operation starts

again.

SH7101 Datasheet(PDF) 83 Page - Renesas Technology Corp