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SH7101 Datasheet(PDF) 124 Page - Renesas Technology Corp |
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SH7101 Datasheet(HTML) 124 Page - Renesas Technology Corp |
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124 / 486 page  7. Bus State Controller (BSC) Rev.2.00 Sep. 27, 2007 Page 90 of 448 REJ09B0394-0200 7.6 On-chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in table 7.2. Table 7.2 On-chip Peripheral I/O Register Access On-chip Peripheral Module SCI MTU, POE INTC PFC, PORT CMT A/D WDT Connected bus width 8 bits 16 bits 16 bits 16 bits 16 bits 8 bits 16 bits Access cycle 2 cycles* 1 2 cycles*1 2 cycles*2 2 cycles*2 2 cycles*1 3 cycles*1 3 cycles*2 Notes: 1. In terms of the peripheral clock value 2. In terms of the system clock value |
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