SH7101 datasheet(222/486 Pages) RENESAS

222 / 486 page

8. Multi-Function Timer Pulse Unit (MTU)

Rev.2.00 Sep. 27, 2007 Page 188 of 448

REJ09B0394-0200

Counter Clearing by another Channel: In complementary PWM mode, by setting a mode for

synchronization with another channel by means of the timer synchro register (TSYR), and

selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it

is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel.

Figure 8.49 illustrates the operation.

Use of this function enables counter clearing and restarting to be performed by means of an

external signal.

TGRA_3

TCDR

TDDR

H'0000

Channel 1

Input capture A

TCNT_1

TCNT_3

TCNT_4

TCNTS

Synchronous counter clearing by channel 1 input capture A

Figure 8.49 Counter Clearing Synchronized with Another Channel

Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In

complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate

control register (TGCR). Figures 8.50 to 8.53 show examples of brushless DC motor drive

waveforms created using TGCR.

When output phase switching for a 3-phase brushless DC motor is performed by means of external

signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external

signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B,

SH7101 Datasheet(PDF) 222 Page - Renesas Technology Corp