3886 datasheet(79/380 Pages) RENESAS

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HARDWARE

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3886 Group User’s Manual

(2) START condition generating procedure using multi-master

1. Procedure example (The necessary conditions of the generat-

ing procedure are described in Items 2 to 5 below.

LDA —

(Taking out of slave address value)

SEI

(Interrupt disabled)

BBS 5, S1, BUSBUSY (BB flag confirming and branch process)

BUSFREE:

STA S0

(Writing of slave address value)

LDM #$F0, S1

(Trigger of START condition generating)

CLI

(Interrupt enabled)

BUSBUSY:

CLI

(Interrupt enabled)

2. Use “Branch on Bit Set” of “BBS 5, $0014, –” for the BB flag

confirming and branch process.

3. Use “STA $12, STX $12” or “STY $12” of the zero page ad-

dressing instruction for writing the slave address value to the

I2C data shift register.

4. Execute the branch instruction of Item 2 and the store instruc-

tion of Item 3 continuously, as shown in the procedure example

above.

5. Disable interrupts during the following three process steps:

• BB flag confirming

• Writing of slave address value

• Trigger of START condition generating

When the condition of the BB flag is bus busy, enable interrupts

immediately.

(3) RESTART condition generating procedure

This procedure cannot be applied to M38867M8A and

M38867E8A when the external memory is used and the bus cycle

is extended by ONW function.

1. Procedure example (The necessary conditions for the proce-

dure are described in items 2 to 4 below.)

Execute the following procedure when the PIN bit is “0.”

LDM #$00, S1

(Select slave receive mode)

LDA —

(Take out of slave address value)

SEI

(Disable interrupt)

STA S0

(Write slave address value)

LDM #$F0, S1

(Trigger RESTART condition generation)

CLI

(Enable interrupt)

2. Select the slave receive mode when the PIN bit is “0.” Do not

write “1” to the PIN bit. Neither “0” nor “1” is specified as input to

the BB bit.

The TRX bit becomes “0” and the SDA pin is released.

3. The SCL pin is released by writing the slave address value to

the I2C data shift register.

4. Disable interrupts during the following two process steps:

• Write slave address value

• Trigger RESTART condition generation

(4) Writing to I2C status register

Do not execute an instruction to set the PIN bit to “1” from “0” and

an instruction to set the MST and TRX bits to “0” from “1” simulta-

neously. Because it may enter the state that the SCL pin is

released and the SDA pin is released after about one machine

cycle. Do not execute an instruction to set the MST and TRX bits

to “0” from “1” simultaneously when the PIN bit is “1.” Because it

may become the same as above.

(5) Process of after STOP condition generating

Do not write data in the I2C data shift register S0 and the I2C sta-

tus register S1 until the bus busy flag BB becomes “0” after

generating the STOP condition in the master mode. Because the

STOP condition waveform might not be normally generated.

Reading to the above registers do not have the problem.

(6) STOP condition input at 7th clock pulse

The SDA line may be held at LOW even if flag BB is set to “0”

when all the following conditions are satisfied:

•In the slave mode

•The STOP condition is input at the 7th clock pulse while receiving

a slave address or data.

•The clock pulse is continuously input.

Countermeasure:

Write dummy data to the I2C shift register or reset the ES0 bit in

the S1D register (ES0 = “L”

→ ES0 = “H”) during a stop condition

interrupt routine with flag PIN = “1”.

Note: Do not use the read-modify-write instruction at this time.

Furthermore, when the ES0 bit is set to “0”, the SDA pin be-

comes a general-purpose port; the port must be set to input

mode or output “H”.

(7) ES0 bit switch

In standard clock mode when SSC = “000102” or in high-speed

clock mode, flag BB may switch to “1” if ES0 bit is set to “1” when

SDA is “L”.

Countermeasure:

Set ES0 to “1” when SDA is “H”.

FUNCTIONAL DESCRIPTION

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