3886 datasheet(22/380 Pages) RENESAS

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3886 Group User’s Manual

List of figures

Fig. 3.1.7 Timing diagram of multi-master I2C-BUS ................................................................ 3-17

Fig. 3.2.1 Power source current characteristic examples (in high-speed mode, A-D conversion

and comparator operating) ........................................................................................ 3-18

Fig. 3.2.2 Power source current characteristic examples (in high-speed mode) ................ 3-18

Fig. 3.2.3 Power source current characteristic examples (in high-speed mode, WAIT execution) . 3-19

Fig. 3.2.4 Power source current characteristic examples (in middle-speed mode) ............ 3-19

Fig. 3.2.5 Power source current characteristic examples (in middle-speed mode, WAIT execution) . 3-20

Fig. 3.2.6 Power source current characteristic examples (in low-speed mode) ................. 3-20

Fig. 3.2.7 Power source current characteristic examples (at reset) ..................................... 3-21

Fig. 3.2.8 Standard characteristic examples of CMOS output port at P-channel drive (Ta=25 °C) .. 3-22

Fig. 3.2.9 Standard characteristic examples of CMOS output port at P-channel drive (Ta=90 °C) ... 3-22

Fig. 3.2.10 Standard characteristic examples of CMOS output port at N-channel drive (Ta=25 °C) ... 3-23

Fig. 3.2.11 Standard characteristic examples of CMOS output port at N-channel drive (Ta=90 °C) .. 3-23

Fig. 3.2.12 Standard characteristic examples of CMOS large current output port at N-channel

drive (Ta=25 °C) ...................................................................................................... 3-24

Fig. 3.2.13 Standard characteristic examples of CMOS large current output port at N-channel

drive (Ta=90 °C) ...................................................................................................... 3-24

Fig. 3.2.14 Standard characteristic examples of CMOS input port at pull-up (Ta=25 °C) .. 3-25

Fig. 3.2.15 Standard characteristic examples of CMOS input port at pull-up (Ta=90 °C) .. 3-25

Fig. 3.2.16 A-D conversion standard characteristics ............................................................... 3-26

Fig. 3.2.17 D-A conversion standard characteristics ............................................................... 3-27

Fig. 3.3.1 Sequence of switch the detection edge .................................................................. 3-30

Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-30

Fig. 3.3.3 Sequence of changing relevant register ................................................................. 3-31

Fig. 3.3.4 Sequence of setting serial I/O1 control register again ......................................... 3-33

Fig. 3.3.5 PWM0 output ............................................................................................................... 3-37

Fig. 3.3.6 Ceramic resonator circuit .......................................................................................... 3-39

Fig. 3.3.7 Initialization of processor status register ................................................................ 3-40

Fig. 3.3.8 Sequence of PLP instruction execution .................................................................. 3-40

Fig. 3.3.9 Stack memory contents after PHP instruction execution ..................................... 3-40

Fig. 3.3.10 Interrupt routine ........................................................................................................ 3-41

Fig. 3.3.11 Status flag at decimal calculations ........................................................................ 3-41

Fig. 3.3.12 Programming and testing of One Time PROM version ...................................... 3-42

Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-44

Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-44

Fig. 3.4.3 Wiring for CNVss pin ................................................................................................. 3-45

Fig. 3.4.4 Wiring for the VPP pin of the One Time PROM version and the EPROM version ... 3-45

Fig. 3.4.5 Bypass capacitor across the Vss line and the Vcc line ....................................... 3-46

Fig. 3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-46

Fig. 3.4.7 Wiring for a large current signal line ...................................................................... 3-47

Fig. 3.4.8 Wiring of RESET pin ................................................................................................. 3-47

Fig. 3.4.9 Vss pattern on the underside of an oscillator ....................................................... 3-48

Fig. 3.4.10 Setup for I/O ports ................................................................................................... 3-48

Fig. 3.4.11 Watchdog timer by software ................................................................................... 3-49

Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-50

Fig. 3.5.2 Structure of Port Pi direction register ..................................................................... 3-50

Fig. 3.5.3 Structure of I2C data shift register ........................................................................... 3-51

Fig. 3.5.4 Structure of I2C address register ............................................................................. 3-51

Fig. 3.5.5 Structure of I2C status register ................................................................................. 3-52

Fig. 3.5.6 Structure of I2C control register ............................................................................... 3-53

Fig. 3.5.7 Structure of I2C clock control register ..................................................................... 3-54

Fig. 3.5.8 Structure of I2C START/STOP condition control register ..................................... 3-55

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