3886 datasheet(18/380 Pages) RENESAS

18 / 380 page

vii

3886 Group User’s Manual

List of figures

Fig. 2.2.2 Structure of Port control register 2 ............................................................................ 2-8

Fig. 2.2.3 Structure of Interrupt source selection register ....................................................... 2-9

Fig. 2.2.4 Structure of Interrupt edge selection register .......................................................... 2-9

Fig. 2.2.5 Structure of Interrupt request register 1 ................................................................. 2-10

Fig. 2.2.6 Structure of Interrupt request register 2 ................................................................. 2-10

Fig. 2.2.7 Structure of Interrupt control register 1 .................................................................. 2-11

Fig. 2.2.8 Structure of Interrupt control register 2 .................................................................. 2-11

Fig. 2.2.9 Interrupt operation diagram ....................................................................................... 2-13

Fig. 2.2.10 Changes of stack pointer and program counter upon acceptance of interrupt request .. 2-14

Fig. 2.2.11 Time up to execution of interrupt processing routine ......................................... 2-15

Fig. 2.2.12 Timing chart after acceptance of interrupt request ............................................. 2-15

Fig. 2.2.13 Interrupt control diagram ......................................................................................... 2-16

Fig. 2.2.14 Example of multiple interrupts ................................................................................ 2-18

Fig. 2.2.15 Connection example and port P3 block diagram when using key input interrupt .. 2-20

Fig. 2.2.16 Registers setting relevant to key input interrupt (corresponding to Figure 2.2.15) ... 2-21

Fig. 2.2.17 Sequence of switching detection edge ................................................................. 2-22

Fig. 2.2.18 Sequence of check of interrupt request bit .......................................................... 2-22

Fig. 2.2.19 Sequence of changing relevant register ............................................................... 2-23

Fig. 2.3.1 Memory map of registers relevant to timers .......................................................... 2-24

Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y ............................................ 2-24

Fig. 2.3.3 Structure of Timer 1 .................................................................................................. 2-25

Fig. 2.3.4 Structure of Timer 2, Timer X, Timer Y ................................................................. 2-25

Fig. 2.3.5 Structure of Timer XY mode register ...................................................................... 2-26

Fig. 2.3.6 Structure of Port control register 2 .......................................................................... 2-27

Fig. 2.3.7 Structure of Interrupt request register 1 ................................................................. 2-28

Fig. 2.3.8 Structure of Interrupt request register 2 ................................................................. 2-28

Fig. 2.3.9 Structure of Interrupt control register 1 .................................................................. 2-29

Fig. 2.3.10 Structure of Interrupt control register 2 ................................................................ 2-29

Fig. 2.3.11 Timers connection and setting of division ratios ................................................. 2-31

Fig. 2.3.12 Relevant registers setting ....................................................................................... 2-31

Fig. 2.3.13 Control procedure ..................................................................................................... 2-32

Fig. 2.3.14 Peripheral circuit example ....................................................................................... 2-33

Fig. 2.3.15 Timers connection and setting of division ratios ................................................. 2-33

Fig. 2.3.16 Relevant registers setting ....................................................................................... 2-34

Fig. 2.3.17 Control procedure ..................................................................................................... 2-34

Fig. 2.3.18 Judgment method of valid/invalid of input pulses ............................................... 2-35

Fig. 2.3.19 Relevant registers setting ....................................................................................... 2-36

Fig. 2.3.20 Control procedure ..................................................................................................... 2-37

Fig. 2.3.21 Timers connection and setting of division ratios ................................................. 2-38

Fig. 2.3.22 Relevant registers setting ....................................................................................... 2-39

Fig. 2.3.23 Control procedure ..................................................................................................... 2-40

Fig. 2.4.1 Memory map of registers relevant to Serial I/O .................................................... 2-42

Fig. 2.4.2 Structure of Transmit/Receive buffer register ........................................................ 2-43

Fig. 2.4.3 Structure of Serial I/O status register ..................................................................... 2-43

Fig. 2.4.4 Structure of Serial I/O1 control register .................................................................. 2-44

Fig. 2.4.5 Structure of UART control register .......................................................................... 2-44

Fig. 2.4.6 Structure of Baud rate generator ............................................................................. 2-45

Fig. 2.4.7 Structure of Serial I/O2 control register .................................................................. 2-45

Fig. 2.4.8 Structure of Serial I/O2 register ............................................................................... 2-46

Fig. 2.4.9 Structure of Interrupt source selection register ..................................................... 2-46

Fig. 2.4.10 Structure of Interrupt edge selection register ...................................................... 2-47

Fig. 2.4.11 Structure of Interrupt request register 1 ............................................................... 2-48

3886 Datasheet(PDF) 18 Page - Renesas Technology Corp

3886 Datasheet(HTML) 18 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL