3886 datasheet(16/380 Pages) RENESAS

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3886 Group User’s Manual

List of figures

CHAPTER 1 HARDWARE

Fig. 1 M38867M8A-XXXHP, M38867E8AHP pin configuration ................................................ 1-3

Fig. 2 M38867E8AFS pin configuration ...................................................................................... 1-3

Fig. 3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration ................................... 1-4

Fig. 4 Functional block diagram ................................................................................................... 1-5

Fig. 5 Part numbering .................................................................................................................... 1-8

Fig. 6 Memory expansion plan ..................................................................................................... 1-9

Fig. 7 740 Family CPU register structure ................................................................................. 1-10

Fig. 8 Register push and pop at interrupt generation and subroutine call ......................... 1-11

Fig. 9 Structure of CPU mode register ..................................................................................... 1-13

Fig. 10 Memory map diagram .................................................................................................... 1-14

Fig. 11 Memory map of special function register (SFR) ........................................................ 1-15

Fig. 12 Port block diagram (1) ................................................................................................... 1-18

Fig. 13 Port block diagram (2) ................................................................................................... 1-19

Fig. 14 Port block diagram (3) ................................................................................................... 1-20

Fig. 15 Port block diagram (4) ................................................................................................... 1-21

Fig. 16 Structure of port I/O related registers ......................................................................... 1-22

Fig. 17 Interrupt control ............................................................................................................... 1-25

Fig. 18 Structure of interrupt-related registers (1) .................................................................. 1-25

Fig. 19 Structure of interrupt-related registers (2) .................................................................. 1-26

Fig. 20 Connection example when using key input interrupt and port P3 block diagram ... 1-27

Fig. 21 Structure of timer XY mode register ............................................................................ 1-28

Fig. 22 Block diagram of timer X, timer Y, timer 1, and timer 2 ......................................... 1-29

Fig. 23 Block diagram of clock synchronous serial I/O1 ........................................................ 1-30

Fig. 24 Operation of clock synchronous serial I/O1 function ................................................ 1-30

Fig. 25 Block diagram of UART serial I/O1 ............................................................................. 1-31

Fig. 26 Operation of UART serial I/O1 function ...................................................................... 1-32

Fig. 27 Structure of serial I/O1 control registers ..................................................................... 1-33

Fig. 28 Structure of serial I/O2 control register ....................................................................... 1-34

Fig. 29 Block diagram of serial I/O2 function .......................................................................... 1-34

Fig. 30 Timing of serial I/O2 function ....................................................................................... 1-35

Fig. 31 PWM block diagram (PWM0) ........................................................................................ 1-36

Fig. 32 PWM timing ..................................................................................................................... 1-37

Fig. 33 14-bit PWM timing (PWM0) .......................................................................................... 1-38

Fig. 34 Interrupt request circuit of data bus buffer ................................................................. 1-39

Fig. 35 Structure of bus interface related register .................................................................. 1-40

Fig. 36 Bus interface device block diagram ............................................................................. 1-41

Fig. 37 Block diagram of multi-master I2C-BUS interface ...................................................... 1-44

Fig. 38 Structure of I2C address register .................................................................................. 1-45

Fig. 39 Structure of I2C clock control register ......................................................................... 1-46

Fig. 40 Structure of I2C control register .................................................................................... 1-47

Fig. 41 Structure of I2C status register ..................................................................................... 1-49

Fig. 42 Interrupt request signal generating timing .................................................................. 1-49

Fig. 43 START condition generating timing diagram .............................................................. 1-50

Fig. 44 STOP condition generating timing diagram ................................................................ 1-50

Fig. 45 START condition detecting timing diagram ................................................................. 1-50

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