3886 datasheet(19/380 Pages) RENESAS

19 / 380 page

viii

3886 Group User’s Manual

List of figures

Fig. 2.4.12 Structure of Interrupt request register 2 ............................................................... 2-48

Fig. 2.4.13 Structure of Interrupt control register 1 ................................................................ 2-49

Fig. 2.4.14 Structure of Interrupt control register 2 ................................................................ 2-49

Fig. 2.4.15 Serial I/O connection examples (1) ....................................................................... 2-50

Fig. 2.4.16 Serial I/O connection examples (2) ....................................................................... 2-51

Fig. 2.4.17 Serial I/O transfer data format ............................................................................... 2-52

Fig. 2.4.18 Connection diagram ................................................................................................. 2-53

Fig. 2.4.19 Timing chart .............................................................................................................. 2-53

Fig. 2.4.20 Registers setting relevant to transmitting side ..................................................... 2-54

Fig. 2.4.21 Registers setting relevant to receiving side ......................................................... 2-55

Fig. 2.4.22 Control procedure of transmitting side .................................................................. 2-56

Fig. 2.4.23 Control procedure of receiving side ...................................................................... 2-57

Fig. 2.4.24 Connection diagram ................................................................................................. 2-58

Fig. 2.4.25 Timing chart .............................................................................................................. 2-58

Fig. 2.4.26 Registers setting relevant to Serial I/O1 .............................................................. 2-59

Fig. 2.4.27 Setting of serial I/O1 transmission data ............................................................... 2-59

Fig. 2.4.28 Control procedure of Serial I/O1 ............................................................................ 2-60

Fig. 2.4.29 Registers setting relevant to Serial I/O2 .............................................................. 2-61

Fig. 2.4.30 Setting of serial I/O2 transmission data ............................................................... 2-61

Fig. 2.4.31 Control procedure of Serial I/O2 ............................................................................ 2-62

Fig. 2.4.32 Connection diagram ................................................................................................. 2-63

Fig. 2.4.33 Timing chart .............................................................................................................. 2-64

Fig. 2.4.34 Relevant registers setting ....................................................................................... 2-64

Fig. 2.4.35 Control procedure of master unit ........................................................................... 2-65

Fig. 2.4.36 Control procedure of slave unit ............................................................................. 2-66

Fig. 2.4.37 Connection diagram (Communication using UART) ............................................ 2-67

Fig. 2.4.38 Timing chart (using UART) ..................................................................................... 2-67

Fig. 2.4.39 Registers setting relevant to transmitting side ..................................................... 2-69

Fig. 2.4.40 Registers setting relevant to receiving side ......................................................... 2-70

Fig. 2.4.41 Control procedure of transmitting side .................................................................. 2-71

Fig. 2.4.42 Control procedure of receiving side ...................................................................... 2-72

Fig. 2.4.43 Sequence of setting serial I/O1 control register again ....................................... 2-74

Fig. 2.5.1 Memory map of registers relevant to I2C-BUS interface ...................................... 2-76

Fig. 2.5.2 Structure of I2C data shift register ........................................................................... 2-76

Fig. 2.5.3 Structure of I2C address register ............................................................................. 2-77

Fig. 2.5.4 Structure of I2C status register ................................................................................. 2-77

Fig. 2.5.5 Structure of I2C control register ............................................................................... 2-78

Fig. 2.5.6 Structure of I2C clock control register ..................................................................... 2-79

Fig. 2.5.7 Structure of I2C START/STOP condition control register ..................................... 2-80

Fig. 2.5.8 Structure of Interrupt source selection register ..................................................... 2-80

Fig. 2.5.9 Structure of Interrupt request register 1 ................................................................. 2-81

Fig. 2.5.10 Structure of Interrupt request register 2 ............................................................... 2-81

Fig. 2.5.11 Structure of Interrupt control register 1 ................................................................ 2-82

Fig. 2.5.12 Structure of Interrupt control register 2 ................................................................ 2-82

Fig. 2.5.13 I2C-BUS connection structure ................................................................................. 2-83

Fig. 2.5.14 I2C-BUS communication format example .............................................................. 2-84

Fig. 2.5.15 RESTART condition of master reception .............................................................. 2-85

Fig. 2.5.16 SCL waveforms when synchronizing clocks ......................................................... 2-86

Fig. 2.5.17 Initial setting example .............................................................................................. 2-88

Fig. 2.5.18 Read Word protocol communication as I2C-BUS master device ....................... 2-89

Fig. 2.5.19 Generating of START condition and transmission process of slave address + write bit .. 2-90

Fig. 2.5.20 Transmission process of command ....................................................................... 2-91

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