3886 datasheet(83/380 Pages) RENESAS

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HARDWARE

1-58

3886 Group User’s Manual

COMPARATOR CIRCUIT

Comparator Configuration

The comparator circuit consists of resistors, comparators, a com-

parator control circuit, the comparator reference input selection bit

(bit 7 of address 001D16), a comparator data register (address

002D16), the comparator reference power source input pin (P00/

P3REF) and analog signal input pins (P30–P37). The analog input

pin (P30–P37) also functions as an ordinary digital port.

Comparator Operation

To activate the comparator, first set port P3 to input mode by set-

ting the corresponding direction register (address 000716) to “0” to

use port P3 as an analog voltage input pin. The internal fixed ana-

log voltage (VCC ✕ 29/32) can be generated by setting “1” to the

comparator reference input selection bit (bit 7) of the serial I/O2

control register (address 001D16). (The internal fixed analog volt-

age becomes about 4.5 V at VCC = 5.0 V.) When setting “0” to the

comparator reference input selection bit, the P00/P3REF pin be-

comes the comparator reference power source input pin and it is

possible to input the comparator reference power source option-

ally from the external. The voltage comparison is immediately

performed by the writing operation to the comparator data register

(address 002D16). After 14 cycles of the internal system clock

(the time required for the comparison), the comparison result is

stored in the comparator data register (address 002D16).

If the analog input voltage is greater than the internal reference

voltage, each bit of this register is “1”; if it is less than the internal

reference voltage, each bit of this register is “0”. To perform an-

other comparison, the voltage comparison must be performed

again by writing to the comparator data register (address 002D16).

Read the result when 14 cycles of

φ or more have passed after the

comparator operation starts. The ladder resistor is turned on dur-

ing 14 cycles of

φ , which is required for the comparison, and the

reference voltage is generated. An unnecessary current is not

consumed because the ladder resistor is turned off while the com-

parator operation is not performed. Since the comparator consists

of capacitor coupling, the electric charge is lost if the clock fre-

quency is low.

Keep that the clock frequency is 1 MHz or more during the com-

parator operation. Do not execute the STP, WIT, or port P3 I/O

instruction.

Fig. 54 Comparator circuit

FUNCTIONAL DESCRIPTION

VSS

VCC

P3 (8)

P37

P36

P30

Comparator reference input selection

bit (bit 7) of serial I/O2 control

Comparator data register

(address 002D16)

Compar-

ator

Ladder resistor

connecting signal

Comparator

control circuit

Comparator connecting

signal

Compar-

ator

Compar-

ator

P00/P3REF

VCC✕29/32

“1”

“0”

Data bus

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