3886 datasheet(23/380 Pages) RENESAS

23 / 380 page

xii

3886 Group User’s Manual

List of figures

Fig. 3.5.9 Structure of Transmit/Receive buffer register ........................................................ 3-55

Fig. 3.5.10 Structure of Serial I/O1 status register ................................................................. 3-56

Fig. 3.5.11 Structure of Serial I/O1 control register ................................................................ 3-56

Fig. 3.5.12 Structure of UART control register ........................................................................ 3-57

Fig. 3.5.13 Structure of Baud rate generator ........................................................................... 3-57

Fig. 3.5.14 Structure of Serial I/O2 control register ................................................................ 3-58

Fig. 3.5.15 Structure of Watchdog timer control register ....................................................... 3-58

Fig. 3.5.16 Structure of Serial I/O2 register ............................................................................. 3-59

Fig. 3.5.17 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-59

Fig. 3.5.18 Structure of Timer 1 ................................................................................................ 3-60

Fig. 3.5.19 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-60

Fig. 3.5.20 Structure of Timer XY mode register .................................................................... 3-61

Fig. 3.5.21 Structure of Data bus buffer register .................................................................... 3-62

Fig. 3.5.22 Structure of Data bus buffer status register ........................................................ 3-62

Fig. 3.5.23 Structure of Data bus buffer control register ....................................................... 3-63

Fig. 3.5.24 Structure of Comparator data register .................................................................. 3-63

Fig. 3.5.25 Structure of Port control register 1 ....................................................................... 3-64

Fig. 3.5.26 Structure of Port control register 2 ....................................................................... 3-64

Fig. 3.5.27 Structure of PWM0H register ................................................................................. 3-65

Fig. 3.5.28 Structure of PWM0L register .................................................................................. 3-65

Fig. 3.5.29 Structure of PWM1H register ................................................................................. 3-66

Fig. 3.5.30 Structure of PWM1L register .................................................................................. 3-66

Fig. 3.5.31 Structure of AD/DA control register ....................................................................... 3-67

Fig. 3.5.32 Structure of AD conversion register 1 .................................................................. 3-67

Fig. 3.5.33 Structure of D-Ai conversion register .................................................................... 3-68

Fig. 3.5.34 Structure of A-D conversion register 2 ................................................................. 3-68

Fig. 3.5.35 Structure of Interrupt source selection register ................................................... 3-69

Fig. 3.5.36 Structure of Interrupt edge selection register ...................................................... 3-69

Fig. 3.5.37 Structure of CPU mode register ............................................................................ 3-70

Fig. 3.5.38 Structure of Interrupt request register 1 ............................................................... 3-71

Fig. 3.5.39 Structure of Interrupt request register 2 ............................................................... 3-71

Fig. 3.5.40 Structure of Interrupt control register 1 ................................................................ 3-72

Fig. 3.5.41 Structure of Interrupt control register 2 ................................................................ 3-72

Fig. 3.5.42 Structure of Flash memory control register .......................................................... 3-73

Fig. 3.5.43 Structure of Flash command register .................................................................... 3-74

Fig. 3.10.1 M38867M8A-XXXHP, M38867E8AHP pin configuration ..................................... 3-89

Fig. 3.10.2 M38867E8AFS pin configuration ............................................................................ 3-89

Fig. 3.10.3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration ........................ 3-90

3886 Datasheet(PDF) 23 Page - Renesas Technology Corp