3886 datasheet(20/380 Pages) RENESAS

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3886 Group User’s Manual

List of figures

Fig. 2.5.21 Transmission process of RESTART condition and slave address + read bit . 2-92

Fig. 2.5.22 Reception process of lower data ........................................................................... 2-93

Fig. 2.5.23 Reception process of upper data .......................................................................... 2-94

Fig. 2.5.24 Generating of STOP condition ............................................................................... 2-95

Fig. 2.5.25 Communication example as slave device ............................................................. 2-96

Fig. 2.5.26 Reception process of START condition and slave address .............................. 2-97

Fig. 2.5.27 Reception process of command ............................................................................. 2-98

Fig. 2.5.28 Reception process of RESTART condition and slave address ......................... 2-99

Fig. 2.5.29 Transmission process of lower data .................................................................... 2-100

Fig. 2.5.30 Transmission process of upper data ................................................................... 2-101

Fig. 2.5.31 Reception of STOP condition ............................................................................... 2-102

Fig. 2.6.1 Memory map of registers relevant to PWM ......................................................... 2-106

Fig. 2.6.2 Structure of Port control register 1 ........................................................................ 2-107

Fig. 2.6.3 Structure of PWM0H register ................................................................................. 2-108

Fig. 2.6.4 Structure of PWM0L register .................................................................................. 2-108

Fig. 2.6.5 Structure of PWM1H register ................................................................................. 2-109

Fig. 2.6.6 Structure of PWM1L register .................................................................................. 2-109

Fig. 2.6.7 Structure of AD/DA control register ....................................................................... 2-110

Fig. 2.6.8 Connection diagram ................................................................................................. 2-111

Fig. 2.6.9 Relevant registers setting ....................................................................................... 2-112

Fig. 2.6.10 Control procedure ................................................................................................... 2-113

Fig. 2.6.11 PWM0 output ........................................................................................................... 2-113

Fig. 2.7.1 Memory map of registers relevant to A-D converter .......................................... 2-114

Fig. 2.7.2 Structure of AD/DA control register ....................................................................... 2-114

Fig. 2.7.3 Structure of A-D conversion register 1 ................................................................. 2-115

Fig. 2.7.4 Structure of A-D conversion register 2 ................................................................. 2-115

Fig. 2.7.5 Structure of Interrupt source selection register ................................................... 2-116

Fig. 2.7.6 Structure of Interrupt request register 2 ............................................................... 2-117

Fig. 2.7.7 Structure of Interrupt control register 2 ................................................................ 2-117

Fig. 2.7.8 Connection diagram ................................................................................................. 2-118

Fig. 2.7.9 Relevant registers setting ....................................................................................... 2-118

Fig. 2.7.10 Control procedure for 8-bit read .......................................................................... 2-119

Fig. 2.7.11 Control procedure for 10-bit read ........................................................................ 2-119

Fig. 2.8.1 Memory map of registers relevant to D-A converter .......................................... 2-121

Fig. 2.8.2 Structure of Port P5 direction register .................................................................. 2-122

Fig. 2.8.3 Structure of AD/DA control register ....................................................................... 2-122

Fig. 2.8.4 Structure of D-Ai converter register ...................................................................... 2-123

Fig. 2.8.5 Peripheral circuit example ....................................................................................... 2-124

Fig. 2.8.6 Speaker output example ......................................................................................... 2-124

Fig. 2.8.7 Relevant registers setting ....................................................................................... 2-125

Fig. 2.8.8 Control procedure ..................................................................................................... 2-126

Fig. 2.9.1 Memory map of registers relevant to bus interface ............................................ 2-128

Fig. 2.9.2 Structure of Data bus buffer register i .................................................................. 2-129

Fig. 2.9.3 Structure of Data bus buffer status register i ...................................................... 2-129

Fig. 2.9.4 Structure of Data bus buffer control register ....................................................... 2-130

Fig. 2.9.5 Structure of Interrupt source selection register ................................................... 2-130

Fig. 2.9.6 Structure of Interrupt request register 1 ............................................................... 2-131

Fig. 2.9.7 Structure of Interrupt control register 1 ................................................................ 2-131

Fig. 2.9.8 Structure of Port control register 2 ........................................................................ 2-132

Fig. 2.9.9 Bus interface block diagram ................................................................................... 2-133

Fig. 2.9.10 Relevant registers setting ..................................................................................... 2-135

Fig. 2.9.11 Control procedure using interrupt ........................................................................ 2-136

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