3886 datasheet(80/380 Pages) RENESAS

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3886 Group User’s Manual

HARDWARE

A-D CONVERTER

[A-D Conversion Register 1,2 (AD1, AD2)]

003516, 003816

The A-D conversion register is a read-only register that stores the

result of an A-D conversion. When reading this register during an

A-D conversion, the previous conversion result is read.

Bit 7 of the A-D conversion register 2 is the conversion mode se-

lection bit. When this bit is set to “0,” the A-D converter becomes

the 10-bit A-D mode. When this bit is set to “1,” that becomes the

8-bit A-D mode. The conversion result of the 8-bit A-D mode is

stored in the A-D conversion register 1. As for 10-bit A-D mode,

10-bit reading or 8-bit reading can be performed by selecting the

reading procedure of the A-D conversion register 1, 2 after A-D

conversion is completed (in Figure 50).

The A-D conversion register 1 performs the 8-bit reading inclined

to MSB after reset, the A-D conversion is started, or reading of the

A-D converter register 1 is generated; and the register becomes

the 8-bit reading inclined to LSB after the A-D converter register 2

is generated.

[AD/DA Control Register (ADCON)] 003416

The AD/DA control register controls the A-D conversion process.

Bits 0 to 2 select a specific analog input pin. Bit 3 signals the

completion of an A-D conversion. The value of this bit remains at

“0” during an A-D conversion, and changes to “1” when an A-D

conversion ends. Writing “0” to this bit starts the A-D conversion.

Comparison Voltage Generator

The comparison voltage generator divides the voltage between

AVSS and VREF into 1024, and outputs the divided voltages in the

10-bit A-D mode (256 division in 8-bit A-D mode).

The A-D converter successively compares the comparison voltage

Vref in each mode, dividing the VREF (see below), with the input

voltage.

• 10-bit A-D mode (10-bit reading)

Vref =

✕ n (n = 0–1023)

• 10-bit A-D mode (8-bit reading)

Vref =

✕ n (n = 0–255)

• 8-bit A-D mode

Vref =

✕ (n–0.5) (n = 1–255)

(n = 0)

Fig. 49 Structure of AD/DA control register

Channel Selector

The channel selector selects one of ports P60/AN0 to P67/AN7,

and inputs the voltage to the comparator.

Comparator and Control Circuit

The comparator and control circuit compares an analog input volt-

age with the comparison voltage, and then stores the result in the

A-D conversion registers 1, 2. When an A-D conversion is com-

pleted, the control circuit sets the A-D conversion completion bit

and the A-D interrupt request bit to “1”.

Note that because the comparator consists of a capacitor cou-

pling, set f(XIN) to 500 kHz or more during an A-D conversion.

VREF

256

VREF

256

Fig. 50 Structure of 10-bit A-D mode reading

VREF

1024

FUNCTIONAL DESCRIPTION

AD/DA control register

(ADCON : address 003416)

Analog input pin selection bits

0 0 0: P60/AN0

0 0 1: P61/AN1

0 1 0: P62/AN2

0 1 1: P63/AN3

1 0 0: P64/AN4

1 0 1: P65/AN5

1 1 0: P66/AN6

1 1 1: P67/AN7

A-D conversion completion bit

0: Conversion in progress

1: Conversion completed

PWM0 output pin selection bit

0: P56/PWM01

1: P30/PWM00

PWM1 output pin selection bit

0: P57/PWM11

1: P31/PWM10

DA1 output enable bit

0: DA1 output disabled

1: DA1 output enabled

DA2 output enable bit

0: DA2 output disabled

1: DA2 output enabled

b2 b1 b0

10-bit reading

(Read address 003816 before 003516)

(Address 003816)

(Address 003516)

8-bit reading (Read only address 003516)

(Address 003516)

b7b6b5b4 b3b2b1b0

Note: Bits 2 to 6 of address 003816 becomes “0”at reading.

b9b8b7b6 b5b4b3 b2

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