33910 datasheet(42/90 Pages) FREESCALE

42 / 90 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33910

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33910G5AC/MC3433910G5AC

High Side Control Register - HSCR

This register controls the operation of the high side drivers.

Writing to this register returns the High Side Status Register

(HSSR).

PWMHSx - PWM Input Control Enable.

This write-only bit enables/disables the PWMIN input pin

to control the respective high side switch. The corresponding

high side switch must be enabled (HSx bit).

1 = PWMIN input controls HSx output.

0 = HSx is controlled only by SPI.

HSx - HSx Switch Control.

This write-only bit enables/disables the corresponding

high side switch.

1 = HSx switch on.

0 = HSx switch off.

High Side Status Register - HSSR

This register returns the status of the high side switches

and is also returned when writing to the HSCR.

High Side thermal shutdown

A thermal shutdown of the high side drivers is indicated by

setting all HSxOP and HSxCL bits simultaneously.

HSxOP - High Side Switch Open-Load Detection

This read-only bit signals that the high side switches are

conducting current below a certain threshold indicating

possible load disconnection.

1 = HSx Open Load detected (or thermal shutdown)

0 = Normal

HSxCL - High Side Current Limitation

This read-only bit indicates that the respective high side

switch is operating in current limitation mode.

1 = HSx in current limitation (or thermal shutdown)

0 = Normal

Timing Control Register - TIMCR

This register allows to configure the watchdog, the cyclic

sense and Forced Wake-up periods. Writing to the Timing

Control Register (TIMCR) will also return the Watchdog

Status Register (WDSR).

CS/WD - Cyclic Sense or Watchdog prescaler select

This write-only bit selects which prescaler is being written

to, the Cyclic Sense/Forced Wake-up prescaler or the

Watchdog prescaler.

1 = Cyclic Sense/Forced Wake-up Prescaler selected

0 = Watchdog Prescaler select

WDx - Watchdog Prescaler

This write-only bits selects the divider for the watchdog

prescaler and therefore selects the watchdog period in

accordance with Table 22. This configuration is valid only if

windowing watchdog is active.

CYSTx - Cyclic Sense Period Prescaler Select

This write-only bits selects the interval for the wake-up

cyclic sensing together with the bit CYSX8 in the

Configuration Register (CFR) (see page 44).

This option is only active if one of the high side switches is

enabled when entering in Stop or Sleep mode. Otherwise, a

timed wake-up is performed after the period shown in

Table 23.

Table 19. High Side Control Register - $6

Write

PWMHS2

PWMHS1

HS2

HS1

Reset

Value

Reset

Condition

POR

POR, Reset mode, ext_reset, HSx

over-temp or (VSOV & HVSE)

Table 20. High Side Status Register - $6/$7

Read

HS2OP

HS2CL

HS1OP

HS1CL

Table 21. Timing Control Register - $A

Write

CS/WD

WD2

WD1

WD0

CYST2

CYST1

CYST0

Reset

Value

-0

Reset

Condition

-POR

Table 22. Watchdog Prescaler

WD2

WD1

WD0

Prescaler Divider

33910 Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc

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