33910 datasheet(84/90 Pages) FREESCALE

84 / 90 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33910

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33910BAC / MC34910BAC

MXx - Analog Multiplexer Input Select

These write-only bits selects which analog input is

multiplexed to the ADOUT0 pin according to Table 54.

When disabled or when in Stop or Sleep mode, the output

buffer is not powered and the ADOUT0 output is left floating

to achieve lower current consumption.

Table 54. Analog Multiplexer Channel Select

Configuration Register - CFR

This register controls the cyclic sense timing multiplier.

HVDD - Hall Sensor Supply Enable

This write-only bit enables/disables the state of the hall

sensor supply.

1 = HVDD on

0 = HVDD off

CYSX8 - Cyclic Sense Timing x 8

This write-only bit influences the Cyclic Sense period as

shown in Table 51.

1 = Multiplier enabled

0 = None

Interrupt Mask Register - IMR

This register allow to mask some of interrupt sources. The

respective flags within the ISR will continue to work but will

not generate interrupts to the MCU. The 5.0 V Regulator

over-temperature prewarning interrupt and under-voltage

(VSUV) interrupts can not be masked and will always cause

an interrupt.

Writing to the interrupt mask register (IMR) will return the

ISR.

HSM - High Side Interrupt Mask

This write-only bit enables/disables interrupts generated in

the high side block.

1 = HS Interrupts Enabled

0 = HS Interrupts Disabled

LINM - LIN Interrupts Mask

This write-only bit enables/disables interrupts generated in

the LIN block.

1 = LIN Interrupts Enabled

0 = LIN Interrupts Disabled

VMM - Voltage Monitor Interrupt Mask

This write-only bit enables/disables interrupts generated in

the voltage monitor block. The only maskable interrupt in the

voltage monitor block is the VSUP over-voltage interrupt.

1 = Interrupts Enabled

0 = Interrupts Disabled

Interrupt Source Register - ISR

This register allows the MCU to determine the source of

the last interrupt or wake-up respectively. A read of the

high, in case there are no other pending interrupts. If there

are pending interrupts, IRQ will be driven high for 10µs and

then be driven low again.

This register is also returned when writing to the interrupt

mask register (IMR).

ISRx - Interrupt Source Register

These read-only bits indicate the interrupt source following

Table 58. If no interrupt is pending than all bits are 0.

In case more than one interrupt is pending, than the

interrupt sources are handled sequentially multiplex.

MX2

MX1

MX0

Meaning

Disabled

Reserved

Die Temperature Sensor

VSENSE input

L1 input

Reserved

Table 55. Configuration Register - $D

Write

CYSX8

Reset

Value

Reset

Condition

POR, Reset

mode or

ext_reset

POR

Table 56. Interrupt Mask Register - $E

Write

HSM

LINM

VMM

Reset Value

Reset Condition

POR

Table 57. Interrupt Source Register - $E/$F

Read

ISR3

ISR2

ISR1

ISR0

33910 Datasheet(PDF) 84 Page - Freescale Semiconductor, Inc

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