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33910 Datasheet(PDF) 16 Page - Freescale Semiconductor, Inc

Part # 33910
Description  LIN System Basis Chip with High
PDF  90 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33910 Datasheet(HTML) 16 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
16
Freescale Semiconductor
33910
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
MC33910G5AC/MC3433910G5AC
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5 V
≤ VSUP ≤ 18 V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE TIMING (SEE Figure 13
)
SPI Operating Frequency
fSPIOP
––
4.0
MHz
SCLK Clock Period
tPSCLK
250
–
N/A
ns
SCLK Clock High Time(42)
tWSCLKH
110
–
N/A
ns
SCLK Clock Low Time(42)
tWSCLKL
110
–
N/A
ns
Falling Edge of CS to Rising Edge of SCLK(42)
tLEAD
100
–
N/A
ns
Falling Edge of SCLK to CS Rising Edge(42)
tLAG
100
–
N/A
ns
MOSI to Falling Edge of SCLK(42)
tSISU
40
–
N/A
ns
Falling Edge of SCLK to MOSI(42)
tSIH
40
–
N/A
ns
MISO Rise Time(42)
CL = 220 pF
tRSO
–
40
–
ns
MISO Fall Time(42)
CL = 220 pF
tFSO
–
40
–
ns
Time from Falling or Rising Edges of CS to:(42)
- MISO Low-impedance
- MISO High-impedance
tSOEN
tSODIS
0.0
0.0
–
–
50
50
ns
Time from Rising Edge of SCLK to MISO Data Valid(42)
0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100 pF
tVALID
0.0
–
75
ns
RST OUTPUT PIN
Reset Low-level Duration After VDD High (see Figure 12)
tRST
0.65
1.0
1.35
ms
Reset Deglitch Filter Time
tRSTDF
350
480
900
ns
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period(43)
External Resistor REXT = 20 kΩ (1%)
External Resistor REXT = 200 kΩ (1%)
Without External Resistor REXT (WDCONF Pin Open)
tPWD
8.5
79
110
10
94
150
11.5
108
205
ms
Notes
42.
This parameter is guaranteed by process monitoring but not production tested.
43.
Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in kΩ)



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