33910 datasheet(44/90 Pages) FREESCALE

44 / 90 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33910

FUNCTIONAL DEVICE OPERATIONS

LOGIC COMMANDS AND REGISTERS

MC33910G5AC/MC3433910G5AC

Configuration Register - CFR

This register controls the Hall Sensor Supply enable/

disable and the cyclic sense timing multiplier.

HVDD - Hall Sensor Supply Enable

This write-only bit enables/disables the state of the hall

sensor supply.

1 = HVDD on

0 = HVDD off

CYSX8 - Cyclic Sense Timing x 8.

This write-only bit influences the cyclic sense and Forced

Wake-up period as shown in Table 23.

1 = Multiplier enabled

0 = None

Interrupt Mask Register - IMR

This register allows masking of some of the interrupt

sources. No interrupt will be generated to the MCU and no

flag will be set in the ISR register. The 5.0V Regulator over-

temperature prewarning interrupt and Under-voltage (VSUV)

interrupts can not be masked and will always cause an

interrupt.

Writing to the IMR will return the ISR.

HSM - High Side Interrupt Mask

This write-only bit enables/disables interrupts generated in

the high side block.

1 = HS Interrupts Enabled

0 = HS Interrupts Disabled

LINM - LIN Interrupts Mask

This write-only bit enables/disables interrupts generated in

the LIN block.

1 = LIN Interrupts Enabled

0 = LIN Interrupts Disabled

VMM - Voltage Monitor Interrupt Mask

This write-only bit enables/disables interrupts generated in

the Voltage Monitor block. The only maskable interrupt in the

Voltage Monitor Block is the VSUP over-voltage interrupt.

1 = Interrupts Enabled

0 = Interrupts Disabled

Interrupt Source Register - ISR

This register allows the MCU to determine the source of

the last interrupt or wake-up respectively. A read of the

high, in case there are no other pending interrupts. If there

are pending interrupts, IRQ will be driven high for 10µs and

then be driven low again.

This register is also returned when writing to the Interrupt

Mask Register (IMR).

ISRx - Interrupt Source Register

These read-only bits indicate the interrupt source following

Table 30. If no interrupt is pending then all bits are 0.

In case more than one interrupt is pending, the interrupt

sources are handled sequentially multiplex.

Table 27. Configuration Register - $D

Write

HVDD

CYSX8

Reset

Value

Reset

Condition

POR, Reset

mode or

ext_reset

POR

Table 28. Interrupt Mask Register - $E

Write

HSM

LINM

VMM

Reset

Value

1111

Reset

Condition

POR

Table 29. Interrupt Source Register - $E/$F

Read

ISR3

ISR2

ISR1

ISR0

33910 Datasheet(PDF) 44 Page - Freescale Semiconductor, Inc

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