AMD-K6 datasheet(108/346 Pages) AMD

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Signal Descriptions

Chapter 5

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

5.13

BREQ (Bus Request)

Output

Summary

BREQ is asserted by the processor to request the bus in order to

complete an internally pending bus cycle. The system logic can

use BREQ to arbitrate among the bus participants. If the

processor does not own the bus, BREQ is asserted until the

processor gains access to the bus in order to begin the pending

cycle or until the processor no longer needs to run the pending

cycle. If the processor currently owns the bus, BREQ is asserted

with ADS #. The processor asserts BREQ for each assertion of

ADS# but does not necessarily assert ADS# for each assertion of

BREQ.

Driven

BREQ is asserted off the same clock edge on which ADS # is

asserted. BREQ can also be asserted off any clock edge,

independent of the assertion of ADS #. BREQ can be negated

one clock edge after it is asserted.

The processor always drives BREQ except in Tri-State Test

mode.

5.14

CACHE# (Cacheable Access)

Output

Summary

For reads, CACHE # is asserted to indicate the cacheability of

the current bus cycle. In addition, if the processor samples

KEN # assert ed, which in dicates t he driven address is

cacheable, the cycle is a 32-byte burst read cycle. For write

cycles, CACHE# is asserted to indicate the current bus cycle is a

modified cache-line writeback. KEN # is ignored during

writebacks. If CACHE # is not asserted, or if KEN # is sampled

negated during a read cycle, the cycle is not cacheable and

defaults to a single-transfer cycle.

Driven and Floated

CACHE# is driven off the same clock edge as ADS# and remains

in the same state until the clock edge on which NA # or the last

expected BRDY# of the cycle is sampled asserted.

CACHE # is floated off the clock edge that BOFF # is sampled

asserted and off the clock edge that the processor asserts HLDA

in recognition of HOLD.

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