UPD78C18 datasheet(28/110 Pages) NEC

28 / 110 page

µPD78C17,78C18

When this is set as general-purpose input/output ports, as with port A, direct bit setting/resetting/ testing

of port C output latch contents is possible by an arithmetic or logical operation instruction without the use

of an accumulator. Data transfer to/from an accumulator is also possible.

•

µPD78C17 MEMORY MAPPING register (MM)

A register which controls internal RAM access permission.

Bit 3 (RAE) of the MEMORY MAPPING register controls whether or not internal RAM is permitted.

When internal RAM is used in external extension and external memory is used in the area, RAE bit

is set to “0” and internal RAM access is prohibited.

Contents of RAE bit is retained, even if RESET signal is input in the normal operation. However, at

power-on reset, RAE bit is undefined and RAE bit should be initialized by an instruction.

Fig. 2-12

µPD78C17 MEMORY MAPPING Register Format

(5)

PF7 to PF0 (PORT F)

µPD78C17

General-purpose input/output ports also used as address bus.

These pins function as address outputs corresponding to the size of externally installed memory accord-

ing to the MODE0 and MODE1 pin settings.

Pins which are not used for address output can be used for general-purpose input/output ports which

have the same port function as for port A. Input/output setting is performed by the MODE F register.

Table 2-3 Operation of

µPD78C17's PF7 to PF0

MODE1

MODE0

PF 7

PF 6

PF 5

PF 4

PF 3

PF 2

PF 1

PF 0

External Address

Space

Port

AB11

AB10

AB9

AB8

4 Kbytes

Port

AB13

AB12

AB11

AB10

AB9

AB8

16 Kbytes

Setting prohibited

AB15 AB14 AB13

AB12 AB11

AB10

AB9

AB8

63 Kbytes

7654321

RAE

Internal RAM Access

Disable

Enable

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