UPD78C18 datasheet(63/110 Pages) NEC

63 / 110 page

µPD78C17,78C18

3.3

MASKABLE INTERRUPT OPERATION

Interrupt requests except non-maskable interrupts and the SOFTI instruction are maskable interrupts which

can be enabled/disabled (IE F/F set/reset) by the EI/DI instructions and can be masked individually by means of

the mask register.

When an external maskable interrupt is recognized as a normal interrupt signal by an active level input for

more than the specified time, an interrupt request flag is set. If an internal interrupt request is generated, an

interrupt request flag is immediately set. Once the interrupt request flag is set, both the external and internal

interrupts are serviced using the following procedure (see Fig. 3-3).

(i) In the EI state (IE F/F = 1), a check is made to see if the interrupt request flag has been set at the end

checked at end of each instruction. If the flag has been set, the interrupt cycle starts. However, interrupt

requests masked by the mask register are not checked.

(ii) If two or more interrupt request flags have been set simultaneously, their priorities are checked. The

interrupt with the highest priority is acknowledged and the others are held pending.

(iii) When an interrupt request is acknowledged, the interrupt request flag is automatically reset. If two types

of interrupt requests with the same priority have both been unmasked by the mask register, the interrupt

request flag is not reset. This is because the two types are identified by software at a later stage.

(iv) When an interrupt request is acknowledged, the IE F/F is reset, and all interrupts except non-maskable

interrupts and the SOFTI instruction are placed in the disabled state (DI state).

(v) The PSW, upper PC byte, and lower PC byte are saved to the stack memory in that order.

(vi) The program jumps to the interrupt address.

These interrupt operations are automatically carried out in 16 states.

The pending interrupt requests are acknowledged if there are no other interrupt requests of higher priority

when interrupts are enabled by execution of the EI instruction.

With maskable interrupts there are two types of interrupt requests with the same priority and same interrupt

address. Unmasking both types, unmasking one type, or masking both kinds can be selected by setting the

mask register.

(1) When both types are unmasked

The corresponding bits of the mask register for two types of interrupt requests are both set to “0”. In this

case, the interrupt request is the logical sum of the two interrupt request flags.

If an interrupt request is acknowledged in accordance with the interrupt operation as a result of setting one

or both interrupt request flags having the same priority and the program jumps to the interrupt address, the

interrupt request flag is not reset. Therefore, the interrupt request is identified by executing a skip instruction

which tests the interrupt request flag at the beginning of the interrupt service routine, and the interrupt request

flag is reset.

(2) When one type is unmasked

For two types of interrupt requests having the same priority, the corresponding bit of the mask register for

the interrupt request to be unmasked is set to “0” and the other bit is set to “1”. In this case, if an interrupt

request is generated by setting the unmasked interrupt request flag and that interrupt request is acknowledged

in accordance with the interrupt operation, the interrupt request flag is automatically reset.

When the masked interrupt request flag is set, that interrupt request is held pending. When the pending

interrupt request is unmasked, it is acknowledged if there are no other interrupt requests of higher priority in

the interrupt enable state.

(3) When both types are masked

The corresponding bits of the mask register for two types of interrupt request are both set to “1”. In this

case, the interrupt requests are held pending are not acknowledged when the interrupt request flag is set.

When the pending interrupt requests are unmasked, they are acknowledged if there are no other interrupt

requests of higher priority in the interrupt enabled state.

UPD78C18 Datasheet(PDF) 63 Page - NEC

UPD78C18 Datasheet(HTML) 63 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL