UPD78C18 datasheet(40/110 Pages) NEC

40 / 110 page

µPD78C17,78C18

(2)

Timer/event counter output mode register (EOM)

This is an 8-bit register which controls the timer/event counters CO0 and CO1 (Counter Output 0, 1)

operating mode.

The timer/event counter output mode register bits 0 and 4 (LO0, LO1) control whether or not LV0 and

LV1 level are output to the CO0 and CO1 pins, bits 1 and 5 (LD0, LD1) control whether or not LV0 and LV1

level are inverted at an output timing specified by the timer/event counter mode register, bits 2, 3, 6, and 7

(LRE0, LRE1, LRE2, LRE3) control LV0 and LV1 setting/resetting.

Bits LO0, LO1, LRE0, LRE1, LRE2, and LRE3 are automatically reset (0) after individual operations.

After RESET input or in the hardware STOP mode, the timer/event counter output mode register is reset

to 00H.

Fig. 2-22 Timer/Event Counter Output Mode Register (EOM) Format

6543210

LRE3

LRE2

LD 1

LO 1

LRE1

LRE0

LD 0

LO 0

LV0 Data Output

Output contents of LV0

No operation

LV0 Level Inversion

Enable

Disable

Setting prohibited

LV0 Set/Reset

No operation

Resets LV0

Sets LV0

LV1Data Output

Output contents of LV1

No operation

LV1 Level Inversion

Enable

Disable

Setting prohibited

LV1 Set/Reset

No operation

Resets LV1

Sets LV1

UPD78C18 Datasheet(PDF) 40 Page - NEC

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