UPD78C18 datasheet(38/110 Pages) NEC

38 / 110 page

µPD78C17,78C18

Next, the operation which outputs a square wave to the CO0 pin is described.

At first, after ECNT is cleared, a count value (ETM0 < ETM1) is set in the ETM0 and ETM1 registers, and data

for LV0 initial status specification and to enable LV0 level inversion is set in the timer/event counter output

mode register.

In the timer/event counter mode register, by setting an input to ECNT to

φ12 (1

µs: 12-MHz operation) internal

clock, the ECNT clear mode to the ECNT and ETM1 register match signal, and CO0 pin output timing to the

ECNT and ETM0 register match signal or ECNT and ETM1 register match signal, the timer/event counter starts

operation.

ECNT is incremented one

φ12 internal clock at a time, the comparator compares incremented ECNT with the

ETM0 and ETM1 registers, and if these match, the match signal (CP0, CP1) is generated. By this match signal,

LV0 level is output to the CO0 pin, and LV0 level is inverted.

ECNT is cleared by the ECNT and ETM1 register match signal (CP1), ECNT increments again from 0000H,

and the above-mentioned steps are repeated (see Fig. 2-20).

Therefore, a programmable square wave which has the ETM0 and ETM1 register count as a pulse width is

output.

Fig. 2-20 Square Wave Output

Remarks

ETM0 register = m

ETM1 register = n

(m < n: m and n are count values.)

Reference

Clock (

φ12)

CP0

CP1

CO0

Start

UPD78C18 Datasheet(PDF) 38 Page - NEC