UPD78C18 datasheet(33/110 Pages) NEC

33 / 110 page

µPD78C17,78C18

(1)

Timer mode register (TMM)

This is an 8-bit register which controls TIMER0, TIMER1, and TIMER F/F operation (see Fig. 2-16).

The timer mode register bits 0 and 1 (TF0, TF1) control the TIMER F/F operating mode, bits 2 and 3

(CK00, CK01) control TIMER0 input clock, bit 4 (TS0) controls TIMER0 operation. Bits 5 and 6 (CK10, CK11)

control TIMER1 input clock, and bit 7 (TS1) controls TIMER1 operation.

TS0 and TS1 bits clear these UPCOUNTERs to 00H by “1”, and stop increment. By changing “1” to “0”,

the UPCOUNTER starts increment from 00H.

The internal clock (

φ3) divides the oscillator frequency by 3, the internal clock (φ12) divides it by 12, and

the internal clock (

φ384) divides it by 384.

After RESET input, the timer mode register is set to FFH, the UPCOUNTERs in TIMER0 and TIMER1 are

cleared in the suspended state, and TIMER F/F is reset.

Fig. 2-16 Timer Mode Register (TMM) Format

765432

TS1

CK11

CK10

TS0

CK01

CK00

TF1

TF0

TIMER0 COMPARATOR match signal

TIMER1 COMPARATOR match signal

Internal clock (

φ3)

TIMER F/F reset

TIMER F/F Input, Operating Mode

TMM

Disable

TIMER0 Input Clock

Internal clock (

φ12)

Internal clock (

φ384)

TI input

TIMER0 Operation

Reset

Increment

TIMER0 COMPARATOR match signal

TIMER0 Input Clock

Internal clock (

φ12)

Internal clock (

φ384)

TI input

TIMER1 Operation

Reset

Increment

UPD78C18 Datasheet(PDF) 33 Page - NEC

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