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UPD78C18 Datasheet(PDF) 43 Page - NEC |
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UPD78C18 Datasheet(HTML) 43 Page - NEC |
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43 / 110 page  43 µPD78C17,78C18 0 0 1 1 0 1 0 1 Fig. 2-25 Serial Mode Register Format in Asynchronous Mode 7654 3210 S 2 S1 EP PEN L 2 L 1 B 2 B 1 SML x1 x16 x64 Clock Rate Character Length 8 bits Setting prohibited Setting prohibited 7 bits 0 1 Parity Enable Disable Enable 0 1 Even Parity Generation/Check Odd number Even number Number of Stop Bits 2 bits Setting prohibited 1 bit Setting prohibited 76543210 0 0 0 0 RxE TxE SK2 SK1 SMH SCK Selection External clock Internal clock (TO output) Internal clock ( φ384) Internal clock ( φ24) Transmission Enable Reception Enable 0 1 1 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 0 Disable Enable Enable Disable |
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