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UPD78C18 Datasheet(PDF) 95 Page - NEC |
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UPD78C18 Datasheet(HTML) 95 Page - NEC |
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95 / 110 page  95 µPD78C17,78C18 MODE1 (M1) X1 PF7 to PF0 PD7 to PD0 ALE Note1 MODE0 (IO/M) tCYC Address (Upper) Address (Lower) tRDH Read Data tLDR tAD tRL tRD tRR tAFR tLA tLL tAR tAL tLR tML tIL tLM tLI Address (Upper) tLDW tLA tLL tAL tWD tDW tWDH tWL tWW tLW tLI tAW tIL Write Data Note2 X1 PF7 to PF0 PD7 to PD0 ALE RD WR MODE0 (IO/M) Note Address (Lower) TIMING WAVEFORM Read Operation Notes 1. When MODE1 pin is pulled up, M1 signal is output to MODE1 pin in the 1st OP code fetch cycle. 2. When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register read cycle. Write Operation Note When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register write cycle. |
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