UPD78C18 datasheet(68/110 Pages) NEC

68 / 110 page

µPD78C17,78C18

4.3

SOFTWARE STOP MODE

When the STOP instruction is executed, the software STOP mode is set unless the interrupt request flag for

an unmasked external interrupt is set. In the software STOP mode, all clocks stop. When this mode is set,

program execution stops and the contents of all registers and internal RAM are retained (the timer upcounter is

cleared to 00H). Only the NMI and RESET signals used to release the software STOP mode are valid, and all

other functions stop.

The statuses of the

µPD78C17 and 78C18 output pins in the software STOP mode are the same as for the

HALT mode, as shown in Table 4-1.

Cautions

Internal interrupts should be masked before executing the STOP instruction to prevent errors

due to an internal interrupt during the oscillation stabilization time at release of the software

STOP mode.

The TIMER1 match signal is used as the signal to start CPU operation to secure an oscillation

stabilization period after the software STOP mode has been released by setting the non-

maskable interrupt request flag. Thus, it is necessary to set a count value in TIMER REG which

takes account of the oscillation stabilization time, and to set the timer mode register to the

timer operating state, before executing the STOP instruction.

4.4

SOFTWARE STOP MODE RELEASE

(1) Release by RESET signal

When the RESET signal changes from the high to low level in the software STOP mode, the software STOP

mode is released and clock oscillation starts as soon as the reset state is set. When the RESET signal is driven

high after oscillation has stabilized, the CPU starts program execution at address 0.

When the RESET signal changes from the high to low level, clock oscillation starts but it takes time for

oscillation to stabilize. The RESET signal low-level width must therefore be longer than the oscillation stabiliza-

tion time.

When the RESET signal is input, the RAM contents are retained but the contents of other registers are

undefined.

Fig. 4-4 Software STOP Mode Release Timing (RESET Input)

CPU

Operation

OSC

RESET

STOP

Address 0 Instruction Execution

If the software STOP mode is released by the RESET signal, program execution starts at address 0 as in the

case of a normal power-on reset. The SB (Standby) flag can be used to identify the program execution mode.

The SB flag is set (1) when the VDD pin rises from the specified low level or below to the specified high level or

above, and is reset (0) by executing a skip instruction. Thus, by testing the SB flag using a skip instruction in

the program executed after RESET input, a set SB flag indicates a power-on start, and a reset SB flag indicates

a start due to release of the software STOP mode.

UPD78C18 Datasheet(PDF) 68 Page - NEC

UPD78C18 Datasheet(HTML) 68 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL