UPD78C18 datasheet(44/110 Pages) NEC

44 / 110 page

µPD78C17,78C18

Receive operation is enabled by setting (1) bit 3 (RxE) of the serial mode register (SMH).

The start bit is confirmed by detecting the low level of RxD input and the low level after 1 or 2 bits.

Reception is performed by sampling character bit, parity bit, and stop bit following the low level. When

data specified in the serial register from RxD is input, data is transferred to the receive buffer. If the receive

buffer is full, the internal interrupt (INTSR) is generated.

By setting (1) bit 1 (MKSR) of the interrupt mask register (MKH), the internal interrupt (INTSR) is

disabled.

In reception, odd or even parity is checked (when PEN bit = 1). If data do not match (parity error), if

stop bit is low (framing error), or if the next data is transferred to the receive buffer when the receive

buffer is full (overrun error), the error flag is set (1).

However, because error interrupt mechanism is not provided, test is executed by the skip instruction

(SKIT, SKNIT).

The serial clock (SCK) can be selected as an external or internal clock by the serial mode register (SMH).

Three types of

φ24, φ384, or TO outputs can be selected as internal clock. This clock can be output to off-

chip. Or the external serial clock can be input.

By using the internal clock (TO output) as SCK, the data transfer speed can be flexibly changed by

program.

The maximum data transfer speed in reception is set by SCK and the clock rate in 12-MHz operation as

shown below.

Internal Clock

Data Transfer

Speed

External Clock

Data Transfer

Speed

SCK

Clock Rate

SCK

500 kbps

125 kbps

31.25 kbps

125 kbps

31.25 kbps

500 kHz

2 MHz

660 kHz

1 MHz

660 kbps

1 MbpsNote1

Notes

1. If data of transfer speed 660 kbps to 1 Mbps is received, 2 stop bits are required.

2. In x1 clock rate, RxD and SCK synchronization needs to be externally established.

For an example, when data is transferred in the data transfer speed of 110 to 9600 bps, when the timer

input clock is set as internal clock (

φ12), the timer count value (C) is shown below.

Data Transfer

Speed (bps)

Oscillation Frequency

(MHz)

7.3728

14.7456

11.0592

9600

4800

2400

1200

600

300

150

110

128

175

C =

–

C =

192

262

–

C =

128

256

370

C =

x1 Note2

x16

x64

UPD78C18 Datasheet(PDF) 44 Page - NEC

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