UPD78C18 datasheet(30/110 Pages) NEC

30 / 110 page

µPD78C17,78C18

Fig. 2-13

µPD78C18 MEMORY MAPPING Register Format

765

43210

RAE

MM2

MM1

MM0

0 0 1

Port

mode

Single

chip

PD7 to PD0 = Extension

mode

PF7 to PF0 = Port mode

PD7 to PD0 = Input port

PF7 to PF0 = Port mode

PD7 to PD0 = Output port

PF7 to PF0 = Port mode

Disable

Enable

Internal RAM Access

•

MODE F register (MF)

The MODE F register specifies port F input/output in the same way as for the MODE A register in

port A. However, contents of the MODE F register corresponding to port F bits specified as address

line by the MEMORY MAPPING register are in the output mode.

After RESET input or in the hardware STOP mode, all the bits of the MODE F register are set (1) and

port F is an input port (high-impedance).

Fig. 2-14 MODE F Register Format

7654321

MF 7

MF 6

MF 5

MF 4

MF 3

MF 2

MF 1

MF 0

(n = 0 to 7)

Extension

mode

Extension

mode

Extension

mode

Exten-

sion

mode

PD7 to PD0 =

PF3 to PF0 =

PF7 to PF4 = Port mode

PD7 to PD0 =

PF5 to PF0 =

PF7 and PF6 = Port mode

16 Kbytes

4 Kbytes

PD7 to PD0 =

PF7 to PF0 =

256 bytes

31 Kbytes

PFn = Output

PFn = Input

UPD78C18 Datasheet(PDF) 30 Page - NEC

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