UPD78C18 datasheet(69/110 Pages) NEC

69 / 110 page

µPD78C17,78C18

CPU

Operation

OSC

INTFNMI

STOP

Interrupt Execution

Wait (Programmable)

Interrupt Routine

TIMER1

Match Signal

(2) Release by interrupt request flag

When the non-maskable interrupt request flag is set in the software STOP mode, the software STOP mode is

released and simultaneously clock oscillation starts. When clock oscillation starts, the timer upcounter starts

counting up from 00H in accordance with the setting before execution of the STOP instruction. CPU operation

is started by a match signal (wait time taking account of the oscillation stabilization time) from the TIMER1

UPCOUNTER. In this case, the UPCOUNTER match signal does not set the interrupt request flag. The timer

mode register of the timer after generation of the match signal is set to FFH and timer operation is stopped.

After the elapse of the oscillation stabilization time, the program jumps to the interrupt address (0004H)

irrespective of the interrupt enabled/disabled (EI/DI) state and without executing the instruction following the

STOP instruction.

FIg. 4-5 Software STOP Mode Release Timing

4.5

HARDWARE STOP MODE

When the STOP signal changes from the high to low level, the hardware STOP mode is set. In this mode all

clocks stop. When the hardware STOP mode is set, program execution stops and the internal RAM contents

just before stoppage are retained, and the STOP signal used to release the hardware STOP mode is valid. All

other functions stop and the reset state is set.

In the hardware STOP mode, the

µPD78C17 and 78C18 output pins become high-impedance.

UPD78C18 Datasheet(PDF) 69 Page - NEC