UPD78C18 datasheet(59/110 Pages) NEC

59 / 110 page

µPD78C17,78C18

(a) REQUEST REGISTER

This register consists of 11 interrupt request flags which are set by the different interrupt requests. A flag is

reset when an interrupt request is acknowledged or a skip instruction (SKIT or SKNIT) is executed. RESET

input resets all flags.

There are 11 types of interrupt request flags.

• INTFNMI

Set (1) by a falling edge input to the NMI pin. Unlike other interrupt request flags, this flag cannot be

tested by a skip instruction.

• INTFT0

Set (1) by TIMER0 COMPARATOR match signal.

• INTFT1

Set (1) by TIMER1 COMPARATOR match signal.

• INTF1

Set (1) by a rising edge input to the INT1 pin.

• INTF2

Set (1) by a falling edge input to the INT2 pin.

• INTFE0

Set (1) by a match signal when timer/event counter ECNT and ETM0 register contents match.

• INTFE1

Set (1) by a match signal when timer/event counter ECNT and ETM1 register contents match.

• INTFEIN

Set (1) by a falling edge of the timer/event counter CI input or timer output (TO).

• INTFAD

Set (1) when A/D converter conversion values are transferred to the four registers CR0 to CR3.

• INTFSR

Set (1) when the serial interface receive buffer becomes full.

• INTFST

Set (1) when the serial interface transmit buffer becomes empty.

(b) MASK REGISTER

This is a 10-bit mask register which handles all interrupt requests except non-maskable interrupts (NMI). It

can be set (1) or reset (0) bit-wise by an instruction. An interrupt request is masked (disabled) or enabled when

the corresponding bit of the mask register is “1” or “0”, respectively.

All bits of the mask register are set by RESET input and all interrupt requests except non-maskable inter-

rupts are masked. All bits of the mask register are set in the hardware STOP mode.

UPD78C18 Datasheet(PDF) 59 Page - NEC