UPD78C18 datasheet(42/110 Pages) NEC

42 / 110 page

µPD78C17,78C18

Start Bit

Parity Bit

Stop Bit

N = 6, 7

(1) Asynchronous mode

In case of the asynchronous mode, clock rate, character length, number of stop bits, parity enable, and

odd or even parity specifications can be controlled by the serial mode register (SML).

Transmission operation is enabled by setting (1) bit 2 (TxE) of the serial mode register (SMH).

If data is written to the transmission buffer by the “MOV TXB, A” instruction and preceding data transfer

is terminated, contents of the transmission buffer are transferred to the serial register automatically. The

start bit (1 bit), parity bit (odd/even number, no parity), and stop bit (1 or 2 bits) are automatically added to

data which is transferred to the serial register. And this data is transmitted from the TxD pin starting from

the least significant bit (LSB).

If the transmit buffer is empty, the internal interrupt (INTST) is generated.

Transmission data is transmitted from the TxD pin at the fall of SCK in the transfer speed of x1, x1/16, or

x1/64 serial clock (SCK).

The maximum data transfer speed in transmission is set by SCK and clock rate in 12-MHz operation as

shown below.

When TxE is “0” or the serial register has no transmitted data, the TxD pin is in the marking state (1).

By setting bit 2 (MKST) of the interrupt mask register (MKH), the internal interrupt (INTST) is disabled.

Fig. 2-24 Asynchronous Data Format

Internal Clock

Data Transfer

Speed

External Clock

Data Transfer

Speed

SCK

Clock Rate

SCK

x16

x64

500 kbps

125 kbps

31.25 kbps

660 kbps

125 kbps

31.25 kbps

500 kHz

660 kHz

2 MHz

UPD78C18 Datasheet(PDF) 42 Page - NEC

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