UPD78C18 datasheet(29/110 Pages) NEC

29 / 110 page

µPD78C17,78C18

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

External Memory

Port

Maximum 256 bytes

Port

AB11

AB10

AB9

AB8

Maximum 4 Kbytes

Port

AB13

AB12

AB11

AB10

AB9

AB8

Maximum 16 Kbytes

AB15

AB14

AB13

AB12

AB11

AB10

AB9

AB8

Maximum 31 Kbytes

µPD78C18

8-bit general-purpose input/output ports also used as address bus.

Can specify input/output bit-wise as general-purpose input/output ports, and address signal is output

according to external extension memory size when the external expansion memory of 256 bytes or greater

is accessed.

This switchover is performed by the MEMORY MAPPING and MODE F registers.

When this is set as general-purpose input/ourput ports, as with port A, direct bit setting/resetting/testing

of port C output latch contents is possible by an arithmetic or logical operation instruction without the use

of an accumulator. Data transfer to/from an accumulator is also possible.

•

µPD78C18 MEMORY MAPPING register (MM)

4-bit register which specifies PD7 to PD0 and PF7 to PF0 port/extension mode and controls internal

RAM access permission.

Bits 0, 1, and 2 (MM0, MM1, MM2) in the MEMORY MAPPING register control specification of PD7

to PD0 port/extension mode, input/output, and PF7 to PF0 address line.

When bits MM1 and MM2 in the MEMORY MAPPING register are “0”, PD7 to PD0 and PF7 to PF0

are set as general-purpose input/output port, input/output of PD7 to PD0 is specified by MM0, and

input/output of PF7 to PF0 is specified by the MODE F register.

4 types of external extension memory (256 bytes, 4 Kbytes, 16 Kbytes, and 31 Kbytes) can be

selected, and ports which are not used for address line are used as general-purpose input/output

ports.

Bit 3 (RAE) of the MEMORY MAPPING register controls whether or not the access to internal RAM is

permitted.

When internal RAM is not used in external extension and external memory uses the area, RAE bit is

set to “0” and internal RAM access is prohibited.

After RESET input or in the hardware STOP mode, bits MM0, MM1, and MM2 of the MEMORY

MAPPING register are reset (0), and PD7 to PD0 become input ports (high-impedance).

Even if the RESET signal is input in the normal operation, contents of the RAE bit are retained.

However, the RAE bit is undefined after power-on reset, the RAE bit should be initialized by an

instruction.

UPD78C18 Datasheet(PDF) 29 Page - NEC

UPD78C18 Datasheet(HTML) 29 Page - NEC

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