SEC2410 datasheet(30/283 Pages) MICROCHIP

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SEC2410/SEC4410

DS00001587C-page 30

 2013 - 2014 Microchip Technology Inc.

The memory sub-system has an arbiter for each ROM or RAM. The typical use is most ICode instruction access occur

to ROM or IRAM, and most data accesses are to DRAM. When code is downloaded to IRAM, or data such as literals

are fetched from ROM or IRAM, there could be contention for access to these memories. The arbiter for each memory

prioritizes the DCode accesses higher than ICode acceses and AHB bus accesses.

The optional AHB slave port may be connected in a system to CR_AHB/SYS_AHB bus (if this is bus matrix). This

enables other AHB masters such as DMA controllers in the system to access processor memory complex. This access

is controllable through programmable memory ranges for security.

The default memory map is shown below. All addresses here are from the processor perspective.

4.4

ARM-M3 AHB System Bus Interface

The ARM-M3 has a AHB-Lite System Bus Master interface (0x20000000 to 0xDFFFFFFF and 0xE0100000 -

0xFFFFFFFF; The ARM can perform 8-bit, 16-bit and 32-bit loads and stores on the System Bus. Instruction fetches

over the System Bus are also supported

4.5

ARM-M3 Registers

4.6

Illegal Address Access

An access on the system AHB bus can generate an illegal address, if any of the following conditions are met:

The device or memory being accessed does not exist.

The device or memory being accessed is turned off.

The access takes more than 511 clock cycles.

If the processor accesses an illegal address the hardware must generate a complete bus error response on the system

AHB bus.

4.7

ARM-M3 Interrupts

After RESET, the interrupt vector table will be located at 00000000h, which is in the Internal ROM.

TABLE 4-1:

ARM-M3 INTERRUPT

Name

ISR

Vector

Priority

Description

Stack Pointer Top

00000000h

Stack Pointer loaded on reset

Reset

00000004h

-3

ARM-M3 Reset

NMI

00000008h

-2

Non maskable interrupt

Hard Fault

0000000Ch

-1

All classes of Fault, when the fault

cannot activate because of priority or the

Configurable Fault handler has been

disabled. This is synchronous

Memory Management

00000010h

Unused

Bus Fault

00000014h

Pre-fetch fault, memory access fault, and

other address/memory related. This is

synchronous when precise and

asynchronous when imprecise.

Usage Fault

00000018h

Usage fault, such as Undefined

instruction executed or illegal state

transition attempt. This is synchronous.

Reserved

7-10

0000001Ch-

00000028H

Reserved

SVCall

0000002Ch

System service call with SVC instruction.

This is synchronous.

Debug Monitor

00000030h

Debug monitor, when not halting. This is

synchronous, but only active when

enabled. It does not activate if lower

priority than the current activation.

Reserved

00000034h

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