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SEC2410 Datasheet(PDF) 34 Page - Microchip Technology |
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SEC2410 Datasheet(HTML) 34 Page - Microchip Technology |
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34 / 283 page  SEC2410/SEC4410 DS00001587C-page 34 2013 - 2014 Microchip Technology Inc. 5.0 ARM-M3 EXTERNAL INTERRUPTS 5.1 General Description The ARM M3 has a closely coupled Nested Vectored Interrupt Controller (NVIC) that supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. The following is a list of the external interrupts used in SEC2410/SEC4410. The interrupt vectors for the external interrupts start at position 16 in the vector table 5.2 Interrupt Summary TABLE 5-1: INTERRUPT LIST IRQ Number Name Description 0 USB_RESET USB Reset from UDC20 1 CLR_STALL USB Clear Stall from UDC20 2 SET_CONF USB Set Config from UDC20 3 SUSPEND USB Suspend from UDC20 4 SET_INTF USB Set Interface from UDC20 5 SETUP USB Setup Packet from UDC20 6 RES_INTR_06 Reserved for future use 7 WAKEUP System Wakeup 8 WQ_FIFO_INTR WQ fifo interrupt 9 TIMER_3 Timer 3 overflow 10 TIMER_2 Timer 2 overflow 11 TIMER_1 Timer 1 overflow 12 TIMER_0 Timer 0 overflow 13 SMART_CARD_INT Smart Card Interrupt 14 UART_INT UART Interrupt 15 AES_UNALIGNED_ACCESS AES Error Interrupt 16 AES_UNDER_RUN AES Error Interrupt 17 SIE_EP3_WR SIE Write Endpoint 18 SIE_EP3_RD SIE Read Endpoint 19 SIE_EP2_WR SIE Write Endpoint 20 SIE_EP2_RD SIE Read Endpoint 21 SIE_EP1_WR SIE Write Endpoint 22 SIE_EP1_RD SIE Read Endpoint 23 SIE_EP0_WR SIE Write Endpoint 24 SIE_EP0_RD SIE Read Endpoint 25 LUN_TIMEOUT FMDU LUN Timeout interrupt 26 AUTO_CBW_INTR Auto CBW processor interrupt 27 FMDU_EP0_WR_INTR FMDU EP0 Write interrupt 28 FMDU_EP0_RD_INTR FMDU EP0 Read interrupt 29 AES_FIFO_OVERFLOW AES FIFO Overflow Interrupt 30 OTP_READY OTP Ready 31 AES_RESIDUAL AES Residual Interrupt 32 RES_INTR_32 Reserved for future use 39 SD1_CMD_ERR From SDC1 |
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